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PRELIMINARY APPLICATION NOTE PMC-1991820 ISSUE 2
PM73122 / PM73123 / PM73124 AAL1GATOR-32 / -8 / -4
PROGRAMMER'S GUIDE
PM73122 / PM73123 / PM73124
AAL1GATOR PRODUCT FAMILY AAL1GATOR-32 / -8 / -4
32 / 8 / 4 LINK CES/DBCES AAL1 SAR
PROGRAMMER'S GUIDE
PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 2: APRIL 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-1991820 ISSUE 2
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PROGRAMMER'S GUIDE
REVISION HISTORY Issue No. 1 2 Issue Date January 2000 April 2001 Details of Change Created document. Corrected Configuration Steps Flow Chart. Clarified tributary mapping in the SBI Extract Tributary Mapping Configuration section. Corrected incorrect reference made in Section 8.4.5 Line Clock Source.
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PROGRAMMER'S GUIDE
CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 1.4 2 3 SCOPE.......................................................................................... 1 TARGET AUDIENCE..................................................................... 1 NUMBERING CONVENTIONS ..................................................... 1 DEVICE NAMING CONVENTIONS .............................................. 1
REFERENCES......................................................................................... 2 AAL1GATOR PRODUCT FAMILY OVERVIEW ....................................... 3 3.1 3.2 3.3 AAL1GATOR-32............................................................................ 3 AAL1GATOR-8.............................................................................. 4 AAL1GATOR-4.............................................................................. 5
4
REGISTER DESCRIPTION ..................................................................... 7 4.1 4.2 MEMORY MAPPED REGISTERS................................................. 8 NORMAL MODE REGISTERS...................................................... 9
5
OPERATIONAL PROCEDURES.............................................................11 5.1 SOFTWARE RESET ....................................................................11 5.1.1 CHIP SOFTWARE RESET................................................11 5.1.2 A1SP SOFTWARE RESET ...............................................11 5.2 CONFIGURATION PROCEDURE............................................... 12 5.2.1 STATE S0: HARDWARE RESET ..................................... 14 5.2.2 STATE S1: CHIP AND A1SP SOFTWARE RESET .......... 14 5.2.3 STATE S2: A1SP SOFTWARE RESET............................ 15 5.2.4 STATE S3: NORMAL OPERATING MODE ...................... 16
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5.3 6
DEVICE IDENTIFICATION.......................................................... 16
CONFIGURING THE UTOPIA INTERFACE .......................................... 17 6.1 6.2 6.3 6.4 COMMON UTOPIA INTERFACE CONFIGURATION.................. 20 UTOPIA SOURCE INTERFACE CONFIGURATION ................... 23 UTOPIA SINK INTERFACE CONFIGURATION .......................... 26 VCI BASED UTOPIA TO UTOPIA LOOPBACK .......................... 29 6.4.1 VCI LOOPBACK SETUP EXAMPLE IN MULTI-ADDRESS MODE............................................................................... 30
7
DATA STRUCTURES............................................................................. 32 7.1 TRANSMIT DATA STRUCTURES............................................... 32 7.1.1 P_FILL_CHAR.................................................................. 34 7.1.2 T_SEQNUM_TBL ............................................................. 35 7.1.3 T_COND_SIG................................................................... 36 7.1.4 T_COND_DATA................................................................ 37 7.1.5 RESERVED (TRANSMIT SIGNALING BUFFER)............. 38 7.1.6 T_OAM_QUEUE .............................................................. 39 7.1.7 T_QUEUE_TBL ................................................................ 40 7.1.8 RESERVED (TRANSMIT DATA BUFFER) ....................... 51 7.2 RECEIVE DATA STRUCTURES ................................................. 52 7.2.1 R_OAM_QUEUE_TBL ..................................................... 55 7.2.2 R_OAM_CELL_CNT ........................................................ 56 7.2.3 R_DROP_OAM_CELL...................................................... 57 7.2.4 R_SRTS_CONFIG............................................................ 57 7.2.5 R_CRC_SYNDROME....................................................... 58
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7.2.6 R_CH_TO_QUEUE_TBL.................................................. 61 7.2.7 R_COND_SIG .................................................................. 64 7.2.8 R_COND_DATA ............................................................... 66 7.2.9 RESERVED (RECEIVE SRTS QUEUE)........................... 67 7.2.10 RESERVED (RECEIVE SIGNALING BUFFER) ............... 68 7.2.11 R_QUEUE_TBL................................................................ 69 7.2.12 R_OAM_QUEUE .............................................................. 85 7.2.13 RESERVED (RECEIVE DATA BUFFER).......................... 86 8 CONFIGURING THE LINE INTERFACE ............................................... 89 8.1 8.2 8.3 CONVENTIONS .......................................................................... 90 REGISTER SUMMARY............................................................... 91 DIRECT LOW SPEED MODE..................................................... 93 8.3.1 LINE FORMAT AND FRAME STRUCTURE ..................... 94 8.3.2 LINE CLOCK SOURCE .................................................... 95 8.3.3 SYNCHRONIZATION ....................................................... 98 8.3.4 CAS SIGNALING............................................................ 100 8.3.5 OTHER PER-LINE OPTIONS ........................................ 102 8.4 SBI MODE................................................................................. 104 8.4.1 PROGRAMMING THE SBI INTERFACE........................ 106 8.4.2 GENERAL SBI CONFIGURATION ................................. 108 8.4.3 EXTRACT SBI BLOCK CONFIGURATION .....................115 8.4.4 INSERT SBI BLOCK CONFIGURATION........................ 128 8.4.5 LINE CLOCK SOURCE .................................................. 141 8.4.6 OTHER PER-LINE OPTIONS ........................................ 142
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8.5
H-MVIP MODE .......................................................................... 143 8.5.1 LINE FORMAT AND FRAME STRUCTURE ................... 144 8.5.2 LINE CLOCK SOURCE .................................................. 144 8.5.3 SYNCHRONIZATION ..................................................... 145 8.5.4 CAS SIGNALING............................................................ 145
8.6
HIGH SPEED MODE ................................................................ 145 8.6.1 HIGH SPEED LINE CONFIGURATION.......................... 146 8.6.2 LINE CLOCK SOURCE .................................................. 147 8.6.3 OTHER PER-LINE OPTIONS ........................................ 148
9
CONFIGURING THE A1SP BLOCKS .................................................. 149 9.1 9.2 9.3 SENDING OAM CELLS ............................................................ 149 ADDING QUEUES .................................................................... 149 A1SP CLOCK CONFIGURATION ............................................. 150
10 11
CONFIGURING THE RAM INTERFACE ............................................. 152 INTERRUPTS ...................................................................................... 154 11.1 11.2 11.3 11.4 11.5 MASTER INTERRUPTS ........................................................... 155 UTOPIA INTERRUPTS ............................................................. 157 RAM INTERFACE INTERRUPTS ............................................. 157 LINE INTERFACE INTERRUPTS ............................................. 157 A1SP INTERRUPTS ................................................................. 157 11.5.1 A1SPN RECEIVE STATUS FIFO ................................... 159 11.5.2 A1SPN TRANSMIT IDLE STATE FIFO .......................... 160 11.5.3 RECEIVE QUEUE ERROR ENABLES........................... 162
12
IDLE CHANNEL DETECTION CONFIGURATION AND STATUS........ 163
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12.1 12.2 12.3 12.4 12.5 12.6 12.7
RECEIVE CHANNEL ACTIVE TABLE....................................... 163 RECEIVE PENDING TABLE ..................................................... 164 RECEIVE CHANGE POINTER TABLE ..................................... 165 TRANSMIT CHANNEL ACTIVE TABLE .................................... 166 PATTERN MATCHING LINE CONFIGURATION ...................... 167 IDLE DETECTION CONFIGURATION TABLE.......................... 168 CAS/PATTERN MATCHING CONFIGURATION ....................... 169 12.7.1 CAS MATCHING FORMAT ............................................ 169 12.7.2 PATTERN MATCHING FORMAT.................................... 170 12.7.3 PROCESSOR IDLE DETECTION FORMAT .................. 170
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PRELIMINARY APPLICATION NOTE PMC-1991820 ISSUE 2
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PROGRAMMER'S GUIDE
LIST OF FIGURES FIGURE 1 - AAL1GATOR-32 BLOCK DIAGRAM .............................................. 4 FIGURE 2 - AAL1GATOR-8 BLOCK DIAGRAM ................................................ 5 FIGURE 3 - AAL1GATOR-4 BLOCK DIAGRAM ................................................ 6 FIGURE 4 - AAL1GATOR MEMORY MAP......................................................... 7 FIGURE 5 - A1SP SRAM MEMORY MAP ......................................................... 8 FIGURE 6 - CONFIGURATION STEPS FLOW CHART .................................. 13 FIGURE 7 - UTOPIA INTERFACE BLOCK DIAGRAM .................................... 19 FIGURE 8 - CELL HEADER INTERPRETATION............................................. 22 FIGURE 9 - UTOPIA LEVEL 2 MULTI-ADDRESS MODE WITH VCI BASED LOOPBACK ...................................................................................................... 31 FIGURE 10 - TRANSMIT DATA STRUCTURES MEMORY MAP .................... 32 FIGURE 11 - SDF-MF FORMAT OF THE T_SIGNALING BUFFER ................ 39 FIGURE 12 - RECEIVE DATA STRUCTURES ................................................ 53 FIGURE 13 - R_CRC_SYNDROME MASK BIT TABLE LEGEND................... 59 FIGURE 14 - LINE INTERFACE BLOCK ARCHITECTURE ............................ 90 FIGURE 15 - CAPTURE OF T1 SIGNALING BITS ....................................... 101 FIGURE 16 - OUTPUT OF T1 SIGNALING BITS .......................................... 101 FIGURE 17 - CAPTURE OF E1 SIGNALING BITS ....................................... 102 FIGURE 18 - OUTPUT OF E1 SIGNALING BITS.......................................... 102 FIGURE 19 - SBI BLOCK ARCHITECTURE ................................................. 105 FIGURE 20 - ADDQ_FIFO WORD STRUCTURE ......................................... 150 FIGURE 21 - INTERRUPT HIERARCHY....................................................... 154
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PROGRAMMER'S GUIDE
LIST OF TABLES FIGURE 1 - AAL1GATOR-32 BLOCK DIAGRAM .............................................. 4 FIGURE 2 - AAL1GATOR-8 BLOCK DIAGRAM ................................................ 5 FIGURE 3 - AAL1GATOR-4 BLOCK DIAGRAM ................................................ 6 FIGURE 4 - AAL1GATOR MEMORY MAP......................................................... 7 FIGURE 5 - A1SP SRAM MEMORY MAP ......................................................... 8 FIGURE 6 - CONFIGURATION STEPS FLOW CHART .................................. 13 FIGURE 7 - UTOPIA INTERFACE BLOCK DIAGRAM .................................... 19 FIGURE 8 - CELL HEADER INTERPRETATION............................................. 22 FIGURE 9 - UTOPIA LEVEL 2 MULTI-ADDRESS MODE WITH VCI BASED LOOPBACK ...................................................................................................... 31 FIGURE 10 - TRANSMIT DATA STRUCTURES MEMORY MAP .................... 32 FIGURE 11 - SDF-MF FORMAT OF THE T_SIGNALING BUFFER ................ 39 FIGURE 12 - RECEIVE DATA STRUCTURES ................................................ 53 FIGURE 13 - R_CRC_SYNDROME MASK BIT TABLE LEGEND................... 59 FIGURE 14 - LINE INTERFACE BLOCK ARCHITECTURE ............................ 90 FIGURE 15 - CAPTURE OF T1 SIGNALING BITS ....................................... 101 FIGURE 16 - OUTPUT OF T1 SIGNALING BITS .......................................... 101 FIGURE 17 - CAPTURE OF E1 SIGNALING BITS ....................................... 102 FIGURE 18 - OUTPUT OF E1 SIGNALING BITS.......................................... 102 FIGURE 19 - SBI BLOCK ARCHITECTURE ................................................. 105 FIGURE 20 - ADDQ_FIFO WORD STRUCTURE ......................................... 150 FIGURE 21 - INTERRUPT HIERARCHY....................................................... 154
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PROGRAMMER'S GUIDE
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PROGRAMMER'S GUIDE
1 1.1
INTRODUCTION Scope The AAL1gator-32/8/4 Programmer's Guide is intended to describe the configurable features and operation of an AAL1gator-32/8/4 from a programmer's perspective. This document may not cover all applications of the AAL1gator-32/8/4. Please contact a PMC-Sierra Applications Engineer for specific uses not covered in this document. This document is a supplement to the AAL1gator-32 [1], AAL1gator-8 [2], and AAL1gator-4 [3] Longform Datasheets. Both the longform datasheet and the programmer's guide should be studied together to interface the AAL1gator-32/8/4 to an embedded processor. In case of a discrepancy between the programmer's guide and the datasheet, the datasheet will take precedence. This document is a supplement to the AAL1gator-32/8/4 Software Driver User's Manual for engineers who need detailed information on register accesses and programming procedures.
1.2
Target Audience This document has been prepared for engineers that design-in the AAL1gator-32/8/4 and require a quick reference for programming the AAL1gator-32/8/4. It is assumed that the reader is familiar with ATM, AAL1, circuit emulation, line interface, and UTOPIA interface technologies.
1.3
Numbering Conventions The following numbering conventions are used throughout this document: * * * Binary Decimal Hexadecimal 1010b, "011", `1' 129, 8 0x80120, 1FH
1.4
Device Naming Conventions From this point forward, the term AAL1gator shall refer to all three of the AAL1gator-32/8/4 variants, while features and functionality specific to each variant shall use the name of the individual device.
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1
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PROGRAMMER'S GUIDE
2
REFERENCES 1. 2. 3. 4. 5. 6. PMC-1981419, PMC-Sierra, Inc., "ATM Adaptation Layer 1 Segmentation and Reassembly Processor-32 Datasheet", September 1999, Issue 2. PMC-2000097, PMC-Sierra, Inc., "ATM Adaptation Layer 1 Segmentation and Reassembly Processor-8 Datasheet", January 2000, Issue 1. PMC-2000098, PMC-Sierra, Inc., "ATM Adaptation Layer 1 Segmentation and Reassembly Processor-4 Datasheet", January 2000, Issue 1. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 1, V. 2.01, Foster City, CA USA, March 1994. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V. 1.0, Foster City, CA USA, June 1995. PMC-1980577, PMC-Sierra, Inc., "SATURN Compatible Scaleable Bandwidth Interconnect (SBI) Specification", October 1998, Issue 3.
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3
AAL1GATOR PRODUCT FAMILY OVERVIEW The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32/8/4) is a highly integrated and flexible monolithic single chip device that provides DS1, E1, DS3, E3, J2 and STS-1/STM-0 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator-32/8/4 device.
3.1
AAL1gator-32 The AAL1gator-32 contains four AAL1 SAR Processors (A1SP) which work in parallel. The A1SP blocks interface to a common UTOPIA interface on one side and a Line Interface block on the other side which can be configured to support direct clock and data, H-MVIP, or SBI mode. Two of the A1SP blocks share one ram interface and the other two A1SP blocks share the other ram interface. The processor Interface block which also contains the external clock control interface is shared by all blocks. The AAL1gator-32 is ideal for applications such as multi-service ATM switches, ATM access concentrators, digital cross connects, computer telephony chassis with an ATM infrastructure, wireless local loop back hauls, and ATM Passive Optical Network equipment. The functional blocks of the AAL1gator-32 are shown in Figure 1.
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Figure 1 - AAL1gator-32 Block Diagram
RAM2_ADSCB RAM2_A[17:0] RAM2_D[15:0] RAM2_PAR[1:0] RAM2_WEB[1:0] RAM2_CSB RAM2_OEB
SYSCLK NCLK TL_CLK_OE TL_CLK[15:0] RL_CLK[15:0] CRL_CLK CTL_CLK
Line Interface Clock MUX
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
RAM2 Interface
32 8
A1SP
8
SBI
LINE_MODE[1:0] ADETECT AACTIVE REFCLK C1FP DDATA[7:0] DDP DPL DV5 ADATA[7:0] ADP AJUST_REQ APL AV5
8
A1SP
8
32
UTOPIA Interface
8
32
H-MVIP Low Speed High Speed
8
F0B TL_DATA[15:0] TL_SYNC[15:0] TL_SIG[15:0] RL_DATA[15:0] RL_SYNC[15:0] RL_SIG[15:0]
A1SP
8 16 16
8
A1SP
2 8
2
JTAG
RAM 1 Interface
Processor Interface
External Clock Interface
RAM1_ADSCB RAM1_A[17:0] RAM1_D[15:0] RAM1_PAR[1:0] RAM1_WEB[1:0] RAM1_CSB RAM1_OEB
3.2
AAL1gator-8 The AAL1gator-8 is a reduced link number version of the AAL1gator-32. The AAL1gator-8 provides low power, DBCES capable, eight link circuit emulation for applications such as Integrated Access Devices (IADs), ATM Multiservice Access Switches, Optical Networking Units and base stations in wireless networks. The AAL1gator-8 provides eight DS1/E1 links or a single DS3/E3/STS-1/STM-0 line interface access to an ATM network. The line interface can be configured to support direct clock and data or H-MVIP mode. The functional blocks of the AAL1gator-8 are shown in Figure 2.
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CGC_DOUT[3:0] CGC_LINE[4:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
A[19:0] D[15:0] ALE WRB RDB CSB ACKB INTB
TRST TDO TDI TMS TCK
4
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Figure 2 - AAL1gator-8 Block Diagram
SYSCLK NCLK TL_CLK_OE TL_CLK[7:0] RL_CLK[7:0] CRL_CLK CTL_CLK
Clock MUX
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
Line Interface
8
H-MVIP
2
F0B TL_DATA[7:0] TL_SYNC[7:0] TL_SIG[7:0] RL_DATA[7:0] RL_SYNC[7:0] RL_SIG[7:0]
8
A1SP
8
UTOPIA Interface
8
Direct
8
JTAG
RAM Interface
Processor Interface
External Clock Interface
RAM1_ADSCB RAM1_A[16:0] RAM1_D[15:0] RAM1_PAR[1:0] RAM1_WEB[1:0] RAM1_CSB RAM1_OEB
3.3
AAL1gator-4 The AAL1gator-4 is a reduced link number version of the AAL1gator-32/8. The AAL1gator-4 provides low power, DBCES capable, four link circuit emulation for applications such as Integrated Access Devices (IADs), ATM Multiservice Access Switches, Optical Networking Units and base stations in wireless networks. The AAL1gator-4 is a pin-compatible version of the AAL1gator-8 with support for four DS1/E1 links or a single DS3/E3/STS-1/STM-0 link. The line interface can be configured to support direct clock and data or H-MVIP mode. The AAL1gator-
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CGC_DOUT[3:0] CGC_LINE[3:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
A[19:0] D[15:0] ALE WRB RDB CSB ACKB INTB
TRST TDO TDI TMS TCK
5
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4 is targeted for low link applications such as Optical Networking Units and base stations in wireless networks. The functional blocks of the AAL1gator-4 are shown in Figure 3. Figure 3 - AAL1gator-4 Block Diagram
RL_CLK[3:0] TL_CLK_OE TL_CLK[3:0]
CRL_CLK
RSTB SCAN_ENABLE TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_FULLB TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_EMB RATM_CLK TPHY_ADD[4:0] 4 F0B 4 TL_DATA[3:0] TL_SYNC[3:0] TL_SIG[3:0] 4 RL_DATA[3:0] RL_SYNC[3:0] 4
CTL_CLK
SYSCLK
NCLK
Clock MUX
Line Interface
LINE_MODE
H-MVIP
UTOPIA Interface A1SP
4
Direct Mode
4
RL_SIG[3:0]
JTAG
RAM Interface
Processor Interface
External Clock Interface
RAM_ADSCB
CGC_DOUT[3:0]
D[15:0]
RAM_PAR[1:0]
RAM_WEB[1:0]
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CGC_LINE[3:0]
CGC_SER_D
TRST
RAM_CSB
TCK
RAM_D[15:0]
A[19:0]
RDB
RAM_A[16:0]
CGC_VALID
ADAP_STB
SRTS_STB
TMS
ACKB
TDO
WRB
CSB
TDI
ALE
RAM_OEB
INTB
6
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4
REGISTER DESCRIPTION The microprocessor interface is used to configure and monitor the AAL1gator. The address signals (A[19:0]) provide an address bus while the bi-directional data signals (D[15:0]) provide a data bus to allow the AAL1gator device to interface to an external microprocessor. Both read and write transactions are supported. The microprocessor interface block provides normal and test mode registers which are internal to the AAL1gator, as well as memory mapped registers which are mostly contained in external SRAM. The normal mode registers and memory mapped registers are required for normal operation. Please refer to the datasheets [1,2,3] for information regarding the test mode registers. Unless otherwise specified, AAL1gator registers are described using the convention REGISTER_NAME (20-bit hexadecimal address). Normal mode registers may be specified by its full name or its mnemonic while memory mapped registers have a mnemonic only. A general memory map for the AAL1gator register set is shown in Figure 4. Figure 4 shows the memory region broken into five blocks. The first four blocks, A1SP0 - A1SP3, are the memory mapped registers which are mostly contained within SRAM. The fifth block, Internal (Normal Mode) Registers, is composed of configuration registers common to the entire chip that are contained internally to the chip. A1SP1 through A1SP3 are only used in the AAL1gator-32. However, the same address space is used in all three devices to maintain software compatibility. Figure 4 - AAL1gator Memory Map
0x00000 0x1FFFF 0x20000 0x3FFFF 0x40000 0x5FFFF 0x60000 0x7FFFF 0x80000 0xBFFFF 0xC0000 0xFFFFF A1SP 0 SRAM A1SP 1 SRAM A1SP 2 SRAM A1SP 3 SRAM Internal Registers Test Registers AAL1gator-32 Only
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4.1
Memory Mapped Registers Memory mapped registers are mostly contained within SRAM and are used for line configuration and configuration of transmit and receive structures for each A1SP. Figure 5 shows the memory map of an A1SP block within the SRAM. In the AAL1gator-32, the four A1SP blocks are identical and are accessed by taking the 17-bit relative address shown in Figure 5 and appending the 2-bit A1SP identifier to the front to select the particular A1SP block. Figure 5 - A1SP SRAM Memory Map
0x00000 0x0001F 0x00020 0x07FFF 0x08000 0x1FFFF Control Registers Transmit Data Structures Receive Data Structures
The 2-bit A1SP identifier, with A[19] = 0, is decoded as follows: * * * * A[18:17] = "00" A[18:17] = "01" A[18:17] = "10" A[18:17] = "11" A1SP0 A1SP1 A1SP2 A1SP3
Notes on Memory Mapped Register Bits: * All memory locations are readable and writable. Although once processing has begun, writing to some locations is restricted to prevent corruption of structures or data buffers used by the AAL1gator. Any restricted locations are designated below. All ports marked as "Reserved" must be initialized to 0 at initial setup. Software modifications to these locations after setup will cause incorrect operation. All read/write port bits marked "Not used" must be written with the value 0 to maintain software compatibility with future versions.
*
*
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* 4.2
All read-only port bits marked "Not used" are driven with a 0 and should be masked off by the software to maintain compatibility with future versions.
Normal Mode Registers Normal mode registers are used to configure and monitor the operation of the AAL1gator. Normal mode registers are selected when A[19] is high and A[18] is low. Table 1 shows the normal mode register memory map along with the section of this document that describes each block of registers. Table 1 - Normal Mode Register Memory Map Address 0x8000X 0x8010X 0x8012X 0x80200 - 0x80FFF 0x81000 - 0x812FF 0x82000 - 0x82FFF Register Description Command Registers RAM Interface Registers UTOPIA Interface Registers Line Interface Registers Interrupt and Status Registers Idle Channel Configuration and Status Registers Section 5, 9 10 6 8 11 12
Notes on Normal Mode Register Bits: * Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero unless stated otherwise. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. All configuration bits that can be written into can also be read back. This allows the processor controlling the AAL1gator to determine the programming state of the block. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. Writing into read-only normal mode register bit locations does not affect AAL1gator operation unless otherwise noted.
*
* *
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*
Certain register bits are reserved. To ensure that the AAL1gator operates as intended, reserved register bits must be written with their default value as indicated by the register bit description.
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5
OPERATIONAL PROCEDURES This section describes the procedure to reset the AAL1gator via software and to initialize the AAL1gator before entering the operating state.
5.1
Software Reset There are two types of software resets in the AAL1gator: the chip software reset and the A1SP software reset.
5.1.1 Chip Software Reset The chip software reset is applied by setting the SW_RESET bit in the Reset and Device ID Register (0x80000). When set, the entire device is held in reset including all other registers. While set, the external SRAM may not be accessed. Applying a chip software reset also puts the A1SPs into a reset state. SW_RESET 0 1 Chip is active. Chip is in reset. Function
Please see State S1 in section 5.2.2 for the effects of a chip software reset and the steps that need to be taken before a chip software reset can be removed. 5.1.2 A1SP Software Reset The A1SP software reset is applied to A1SPn by setting the An_SW_RESET bit in the A1SPn Command Register (0x80010, ...,13). When set, the corresponding A1SP is held in reset. An_SW_RESET 0 1 A1SPn is active. A1SPn is in reset. Function
Please see State S2 in section 5.2.3 for the effects of an A1SP software reset and the steps that need to be taken before an A1SP software reset can be removed.
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5.2
Configuration Procedure This section describes the procedure necessary to initialize the AAL1gator after a hardware reset (i.e. - initial power up) and to change the configuration of the AAL1gator at any time. A description of each programming state that exists in the process is provided along with the steps necessary to proceed to the next state. A flow chart of the sequence of steps is shown in Figure 6. As shown, the three reset states are automatically entered when a hardware reset, chip software reset, or A1SPn software reset is applied. Note: The configuration procedure described is the recommended procedure for programming the AAL1gator. For questions relating to alternative sequences for programming the AAL1gator, please contact a PMC-Sierra Applications Engineer.
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Figure 6 - Configuration Steps Flow Chart
Entire Chip Per A1SP
(n = 0, ..., 3)
Hardware Reset
S0: Hardware Reset S2: A1SPn Software Reset Set Up LINE_MODE Hardware Pins
A1SPn Software Reset
Clear A1SPn SRAM to all zeros
Clear Hardware Reset Initialize Transmit and Receive Data Structures Chip Software Reset S1: Chip and A1SP Software Reset
Configure Internal Line S2: A1SP Software Interface Software Reset S2: A1SPRegisters Reset S2: A1SP Software Reset Configure LIN_STR_MODE and HS_LIN_REG No
Poll RUN bit in DLL_STAT_REG
Is bit set?
Set An_CMDREG_ATTN, A1SPn reads configuration
Yes Clear Chip Software Reset
Clear A1SPn Software Reset
Configure UTOPIA Registers
S3: Normal Operation
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5.2.1 State S0: Hardware Reset The hardware reset state is entered when the RSTB input pin is forced low. This state has the following characteristics: * * * All internal registers (0x80000 - 0xBFFFF) are reset to their default states. The UTOPIA Interface powers up with all outputs tri-stated. The TLCLK_OE input pin controls whether or not the TL_CLK lines are inputs or outputs between the time of hardware reset and the reading of the CLK_SOURCE_TX bits in step 5 of State S2.
The following steps need to be taken to proceed to the next state: 1. The line mode of operation needs to be setup. The LINE_MODE input pins should be tied to a certain level at initial hardware reset and not be changed while out of the reset state. See section 8 for the encoding of the LINE_MODE pins. The line mode cannot be changed by software. 2. Take the AAL1gator out of hardware reset by forcing the RSTB pin high. 5.2.2 State S1: Chip and A1SP Software Reset The Chip Software Reset state is automatically entered after a hardware reset is removed, or it can be asserted by setting the SW_RESET bit in the Reset and Device ID Register (0x80000). All A1SPs are also automatically reset when this state is entered. This state has the following characteristics: * * * The entire chip with the exception of the microprocessor interface and the DLL are in reset. The chip is inactive and not processing data. External memory can not be accessed. Changes to internal registers will not take effect until the Chip Software Reset is removed.
The following steps need to be taken to proceed to the next state: 1. Wait two clock periods of the slowest clock before attempting to write to any other register. An exception to this rule is the DLL register port. 2. Poll the RUN bit in the DLL Control Status Register (0x84003) until this bit is set. This ensures that the internal SYSCLK is aligned with the external SYSCLK before proceeding.
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3. Configure the UTOPIA Interface registers. See section 6 for a detailed description of configurable features of the UTOPIA Interface. 4. Remove the Chip Software Reset by writing a 0 to the SW_RESET bit in the Reset and Device ID Register (0x80000). 5.2.3 State S2: A1SP Software Reset All A1SPs are still in software reset after a Chip Software Reset is removed. An individual A1SP can also enter the A1SP Software Reset state by setting the An_SW_RESET bit in the corresponding A1SPn Command Register (0x80010, ... 13). This state has the following characteristics: * * External memory can now be accessed. The line interface is configured in the mode indicated by the LINE_MODE pins but will only be driving data as if all lines and/or queues are disabled.
The following steps need to be taken for each A1SP in reset before entering the normal operating mode: 1. Clear the section of memory allocated to the reset A1SP to all zeros. If all A1SPs are in reset, then clear the entire SRAM to all zeros. See Figure 4 for the memory map of the AAL1gator. A number of data structures used by the device in reserved areas depends on this initialization. See section 7 for a detailed description of these register accesses. 2. Initialize the transmit and receive data structures by writing to registers with an address offset of 0x00020 - 0x1FFFF in each A1SP SRAM memory map. Some memory locations must only be set up in this state (such as T_SEQNUM_TBL and R_CRC_SYNDROME) while others can also be changed during normal operation. See section 7 for the description of transmit and receive data structures. See Figure 5 for the A1SP SRAM memory map. 3. Configure the internal line interface registers. See section 8 for a detailed description of configurable features of the Line Interface. 4. Initialize the memory mapped registers (LIN_STR_MODE and HS_LIN_REG) which contain the line configuration. See section 8 for a detailed description of these register accesses. 5. Set the An_CMDREG_ATTN bit in the A1SPn Command Register (0x80010, ... 13) so that the configuration data written to the LIN_STR_MODE registers and HS_LIN_REG can be read by the A1SP.
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6. Poll the An_CMDREG_ATTN until a `0' is read back to ensure that the configuration read operation is complete. 7. Remove the A1SP Software Reset by writing a `0' to the An_SW_RESET bit in the A1SPn Command Register (0x80010, ... 13). 5.2.4 State S3: Normal Operating Mode After removing the A1SP Software Reset(s), the device reads the data structures from memory and enters the correct operating mode. The R_CH_TO_QUEUE_TBL will then begin a 640 SYSCLK cycle initialization, which resets each timeslot to playing out conditioned data. At this point the queues can be initialized as needed. Queues are added by writing to the An_ADDQ_REG (0x80020, ..., 23) with the number of the queue to be added. There is one add queue FIFO per A1SP. See section 9.2 for details. Note: Once processing has begun, writing to some locations is restricted to prevent corruption of structures or data buffers used by the AAL1gator. 5.3 Device Identification Software can identify the AAL1gator by reading the DEV_ID[3:0] and the DEV_TYPE[2:0] bits in the Reset and Device ID Register (0x80000). The DEV_ID bits can be read to provide a binary number indicating the feature version of the AAL1gator device. These bits are incremented only if features are added in a revision of the chip. The DEV_TYPE bits can be read to distinguish the particular AAL1gator device from the other members of the AAL1gator family of devices as shown in Table 2. Table 2 - DEV_TYPE Encoding Device AAL1gator-4 AAL1gator-8 AAL1gator-32 DEV_TYPE[2:0] 001 010 011
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6
CONFIGURING THE UTOPIA INTERFACE The UTOPIA Interface (UI) manages and responds to all control signals on the UTOPIA bus and passes cells to and from the UTOPIA bus and the four or one A1SP blocks. Both 8-bit and 16-bit UTOPIA interfaces with an optional single parity bit are supported. An 8-bit or 16-bit Any-PHY slave interface is also supported. Each direction can be configured independently and has its own configuration registers. The following UTOPIA/Any-PHY modes are supported. * * * * UTOPIA Level One ATM, Master (8-bit only) UTOPIA Level One PHY, Slave (8 or 16-bit) UTOPIA Level Two PHY, Slave (8 or 16-bit) Any-PHY (8 or 16-bit) Slave
UTOPIA Level 1 UTOPIA Level 1 defines the interface between the Physical Layer (PHY) and upper layers such as the ATM Layer and various management entities. The definition allows a common PHY interface in ATM subsystems across a wide range of speeds and media types up to OC-3c rates (155 Mbps). UTOPIA Level 1 has the restriction that only one PHY device can be supported [4]. The AAL1gator devices can be configured as an 8-bit UTOPIA Level 1 Master or an 8-bit or 16-bit UTOPIA Level 1 Slave. UTOPIA Level 2 UTOPIA Level 2 enhances UTOPIA Level 1 by defining the physical operation of the interface to support up to 31 PHY devices with an aggregate data rate of up to 622 Mbps [5]. With the AAL1gator-32 in UTOPIA Level 2 mode, the device generally responds on the UTOPIA bus as a single port device. However it is possible to configure the sink direction (i.e. the direction from UTOPIA to AAL1gator) as a 4-port device where each A1SP is a different port.
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Any-PHY The Any-PHY interface is a 16 bit, 52 MHz bus that can support up to 832 Mbps of raw bandwidth. By using very few overhead cycles to transmit and receive packets the Any-PHY interface is suitable for designs that need to scale up to OC-12 (622 Mbps) bandwidths. Like POS-PHY and UTOPIA bus interfaces, the Any-PHY interface is a master/slave bus. An Any-PHY bus master can interface with multiple devices. The Any-PHY interface extends beyond the 31 PHY device limit of UTOPIA Level 2 through the use of in-band addressing. One extra word indicating the port address, is prepended to the front of each cell that is transmitted and received. The AAL1gator devices all support the Any-PHY interface. Block Diagram The UI block consists of 6 functions: UI Data Source Interface (SRC_INTF), UI Data Sink Interface(SNK_INTF), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, and UI_REG. See Figure 7 for the block diagram of the AAL1_UI block.
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Figure 7 - UTOPIA Interface Block Diagram
UTOPIA Interface (UI) Block UMUX SRC_INTF FF4CELL
MU X Signals to/from each A1SP block
TXUTOPIA SIGNALS
TX UTOPIA Interface and FIFO Output Logic FF3CELL
Prioritization and FIFO Input Logic
SNK_INTF FF4CELL RX UTOPIA Interface and FIFO Input Logic
DE MU X
Signals to/from each A1SP block
RXUTOPIA SIGNALS
DEMUX and FIFO Output Logic UI_REG
There is very little setup required to configure the UTOPIA Interface. For typical operation, the UI_COMN_CFG_REG, UI_SRC_CFG_REG, and UI_SNK_CFG_REG need to be written to select the mode of operation and the UI_SRC_ADD_CFG and UI_SNK_ADD_CFG need to be programmed for a predefined address of the device. Once the registers are written with the proper configuration information, the UI_EN bit in UI_COMN_CFG_REG should be set to enable normal operation. Aside from the normal configurations, the block can also be placed in loopback where cells received on the UI interface are transmitted back out onto the UI interface. The following registers control the configuration of the UTOPIA interface:
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Address 0x80120 0x80121 0x80122 0x80123 0x80124 0x80125 6.1
Register Description UTOPIA Common Configuration Register UTOPIA Source Configuration Register UTOPIA Sink Configuration Register UTOPIA Source Address Configuration Register UTOPIA Sink Address Configuration Register UTOPIA to UTOPIA Loopback VCI Register
Register Mnemonic UI_COMN_CFG UI_SRC_CFG UI_SNK_CFG UI_SRC_ADD_CFG UI_SNK_ADD_CFG UI_U2U_LOOP_VCI
Common UTOPIA Interface Configuration General configuration and enabling of the UTOPIA Interface is controlled by the UI Common Configuration Register (0x80120). Please note that every time the UTOPIA Interface needs to be reprogrammed, it is recommended to be in the Chip Software Reset state as described in section 5.2.2. The default configuration is as follows: Bit UI_EN U2U_LOOP SHIFT_VCI Register UI Common Configuration Register (0x80120) UI Common Configuration Register (0x80120) UI Common Configuration Register (0x80120) Value 0 0 0 0 0
VCI_U2U_LOOP UI Common Configuration Register (0x80120) VPI_MODE_EN UI Common Configuration Register (0x80120)
The UTOPIA Interface is disabled in the default state. In addition, the remote loopback and VCI based loopback modes are disabled, and neither VCI shifting nor VP mode is used for cell header interpretation. Enabling the UTOPIA Interface The UI_EN bit enables both the source side and sink side UTOPIA Interface. This bit resets to the disabled state so that the chip resets with all UTOPIA outputs tristated. Once the modes have been configured and the interface
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enabled, then the outputs will drive to their correct values. The other UI registers are not affected by this bit. UI_EN 0 Function The UI is disabled. All of the UI logic is held in reset and all of the FIFOs are cleared. The AAL1gator will not respond in the UTOPIA interface. The UI is enabled in both directions.
1
UTOPIA to UTOPIA Loopback Modes The AAL1gator supports two forms of UTOPIA to UTOPIA loopback; global loopback, where all cells are looped, and VC based loopback, where only a specific VC is used to loopback cells. The 3-cell FIFO is used for loopback. In global loopback mode, all cells received by the UTOPIA block are sent back out onto the UTOPIA bus (regardless of single or multi-addressing mode). Global loopback is enabled by setting the U2U_LOOP bit: U2U_LOOP 0 1 The UI is in normal mode. The UI is in global loopback mode Function
In VCI based loopback mode, any cell received with a VCI that matches the loopback VCI is sent back out onto the UTOPIA bus. The loopback VCI is programmable by writing the U2U_LOOP_VCI register (please see section 6.4). VCI based loopback is enabled by setting the VCI_U2U_LOOP bit: VCI_U2U_LOOP 0 1 Function The UI is in normal mode. The UI is in VCI based loopback mode
Cell Header Interpretation The UMUX blocks serves as the bridge between the four or one A1SP blocks and the SNK_INTF and SRC_INTF blocks.
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To determine which A1SP to forward a received cell, the UMUX looks at the VPI and VCI bits of each cell (unless in UTOPIA Level 2 multi-port mode or Any-PHY mode, in which case the bottom two address bits are used). The SHIFT_VCI and VP_MODE_EN bits determine the interpretation of the VCI and VPI bits of the cell header, as shown in Figure 8. Figure 8 - Cell Header Interpretation
SHIFT_VCI=0 VP_MODE_EN=0
15 14 13 Ignored 12 11 10 9 8 7 6 5 Ignored 11 10 A1SP 9 8 Data 7 6 Line 5 4 3 2 1 0 4 3 2 1 0
Queue MOD 32
SHIFT_VCI=1 VP_MODE_EN=0
15 Ignored 14 13 A1SP 12 Data
11
10
9
8
7
6
5 Ignored
4
3
2
1
0
11
10 Line
9
8
7
6
5
4
3 Ignored
2
1
0
Queue MOD 32
SHIFT_VCI=X VP_MODE_EN=1
15 14 13 12
11
10
9
8 Ignored
7
6
5
4 A1SP
3
2
1 Line
0
11
10 Ignored
9
8
7
6 Ignored
5
4
3
2 Ignored
1
0
The three possible interpretations are described below: 1. When SHIFT_VCI is low and VP_MODE_EN is low: * * * VCI[10:9] is used to select the A1SP When VCI[8] is set, the cell is a data cell; when VCI[8] is low, the cell is an OAM cell VCI[7:0] is used as the queue number if VCI[8] = 1
2. When SHIFT_VCI is set and VP_MODE_EN is low: * VCI[14:13] is used to select the A1SP
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* *
When VCI[12] is set, the cell is a data cell; when VCI[12] is low, the cell is an OAM cell VCI[11:4] is used as the queue number if VCI[12] = 1
3. When VP_MODE_EN is set: * * * * VPI[4:3] is used to select the A1SP VPI[2:0] selects the line within the A1SP Queue 0 will be assumed and no VCI bits need to be used to indicate queue number If VCI <= 31, then interpret the cell as an OAM cell and place it in the OAM buffer
Note: VP_MODE_EN can only be set if all lines are in UDF mode. 6.2 UTOPIA Source Interface Configuration The UTOPIA Source Interface (SRC_INTF) block conveys the cells received from the UMUX block to the UTOPIA interface. Configuration of the UTOPIA source side interface is controlled by the UI Source Configuration Register (0x80121). Please note that every time the UTOPIA Interface needs to be reprogrammed, it is recommended to be in the Chip Software Reset state as described in section 5.2.2. The default configuration is as follows: Bit ANY-PHY_EN EVEN_PAR 16_BIT_MODE CS_MODE_EN Register Value 00 0 0 0 0 0x0000
UTOP_MODE[1:0] UI Source Configuration Register (0x80121) UI Source Configuration Register (0x80121) UI Source Configuration Register (0x80121) UI Source Configuration Register (0x80121) UI Source Configuration Register (0x80121)
CFG_ADDR[15:0] Slave Source Address Configuration Register (0x80123)
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In the default state, the source side interface is in UTOPIA Level 1 Master mode with odd parity generation. Source Side Operating Mode Depending on the value of UTOP_MODE[1:0] field, the UTOPIA interface will either act as a UTOPIA master (controls the write enable signal) or as a UTOPIA PHY device (controls the cell available signal). As a PHY device the SRC_INTF can either be a UTOPIA Level 1 device, where it is the only device on the UTOPIA bus, or a UTOPIA Level 2 device where other devices can coexist on the UTOPIA bus. As a master device the SRC_INTF can only function as a UTOPIA Level 1 device. If ANY-PHY_EN is set then the SRC_INTF operates as a single port Any-PHY slave device. In Any-PHY mode in-band addressing is used to allow more than the 32 possible addresses available in UTOPIA mode. One extra word is prepended to the front of each cell that is transmitted. The prepended word indicates the port address sending the cell. The SRC_INTF uses CFG_ADDR[15:0] in the UI_SRC_ADD_CFG register (0x80123) for the address prepend. The operating mode for the source side interface is configured using the UTOP_MODE[1:0], ANY-PHY_EN, and 16_BIT_MODE bits, as summarized in the table below. A "" denotes that the field is selectable for that mode. An "n/a" denotes that the field is ignored for that mode. Mode UTOPIA Level 1 Master UTOPIA Level 1 Slave UTOPIA Level 2 Single Address Slave Any-PHY Slave Notes: * * In the source side interface, UTOP_MODE[1:0] = "11" is Reserved and should not be used. If 16_BIT_MODE is set, then all 16 bits of the UTOPIA data bus or Any-PHY interface are used. UTOP_MODE[1:0] ANY-PHY_EN 00 01 10 n/a 0 0 0 1 16_BIT_MODE 0
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*
If 16_BIT_MODE is low, then only the lower 8 bits are used.
Parity Generation The EVEN_PAR bit determines the calculated parity across data bytes/words sent out of the source interface. EVEN_PAR 0 1 Odd parity Even parity. Function
Chip Select Enable for Any-PHY Mode The CS_MODE_EN bit is used to determine the use of the RPHY_ADDR(3)/RCSB input pin. This bit should only be set in Any-PHY mode. CS_MODE_EN 0 1 Function The RPHY_ADDR(3)/RCSB input pin is used as an address bit (RPHY_ADDR(3)) for the source side interface. The RPHY_ADDR(3)/RCSB input pin is used as a chip select (RCSB) for the source side interface.
Slave Source Address The CFG_ADDR[15:0] bits of the Slave Source Address Configuration Register (0x80123) contain the configured slave address used for UTOPIA Level 2 and Any-PHY operation in the source direction. Depending on the mode of the UTOPIA/Any-PHY interface different bits of this field are used. See the following table for details.
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Polling MODE UTOPIA-2 Single-Addr Any-PHY with CSB Any-PHY without CSB Notes: * PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR [4:0]=device [2:0]=device
Selection PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR is prepended CFG_ADDR [4:0]=device [15:0]=device
[3:0]=device
[3:0]=device
[3:0]=device CFG_ADDR is prepended
[15:0]=device
In Any-PHY mode in the SRC direction, the AAL1gator will prepend the cell with CFG_ADDR[15:0]. In 8-bit mode, the cell will be prepended with CFG_ADDR[7:0]. In Any-PHY mode, if CS_MODE_EN = '0', then CFG_ADDR[4:3] = "00". In Any-PHY mode, if CS_MODE_EN = '1', then CFG_ADDR[3]="0".
* * 6.3
UTOPIA Sink Interface Configuration The UTOPIA Sink Interface (SNK_INTF) block receives cells from the UTOPIA interface and sends them to the UMUX interface. Configuration of the UTOPIA sink side interface is controlled by the UI Sink Configuration Register (0x80122). Please note that every time the UTOPIA Interface needs to be reprogrammed, it is recommended to be in the Chip Software Reset state as described in section 5.2.2. The default configuration is as follows: Bit ANY-PHY_EN EVEN_PAR Register Value 00 0 0
UTOP_MODE[1:0] UI Sink Configuration Register (0x80122) UI Sink Configuration Register (0x80122) UI Sink Configuration Register (0x80122)
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Bit 16_BIT_MODE CS_MODE_EN
Register UI Sink Configuration Register (0x80122) UI Sink Configuration Register (0x80122)
Value 0 0 0x0000
CFG_ADDR[15:0] Slave Sink Address Configuration Register (0x80124)
In the default state, the sink side interface is in UTOPIA Level 1 Master mode with odd parity generation. Sink Side Operating Mode Depending on the value of the UTOP_MODE[1:0] field, the UTOPIA interface acts either as a UTOPIA master (controls the read enable signal) or as a UTOPIA PHY device (controls the cell available signal). As a PHY device the SNK_INTF can either be a UTOPIA Level 1 device, where it is the only device on the UTOPIA bus, or a UTOPIA Level 2 device where other devices can coexist on the UTOPIA bus. As a master device the SNK_INTF can only function as a UTOPIA Level 1 device. If ANY-PHY_EN is set then the SNK_INTF operates as a multi port Any-PHY slave device. In Any-PHY mode in-band addressing is used to allow more than the 32 possible addresses available in UTOPIA mode. One extra word is prepended to the front of each cell that is transmitted. The prepended word indicates the port address to receive the cell. The SNK_INTF uses CFG_ADDR[15:2] in the UI_SNK_ADD_CFG register (0x80124) to match with the address prepend. If 16_BIT_MODE is low then CFG_ADDR(7:2) is used. The operating mode for the sink side interface is configured using the UTOP_MODE[1:0], ANY-PHY_EN, and 16_BIT_MODE bits, as summarized in the table below. A "" denotes that the field is selectable for that mode. An "n/a" denotes that the field is ignored for that mode. Mode UTOPIA Level 1 Master UTOPIA Level 1 Slave UTOPIA Level 2 Single Address Slave UTOPIA Level 2 Multi-Address Slave UTOP_MODE[1:0] ANY-PHY_EN 00 01 10 11 0 0 0 0 16_BIT_MODE 0
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Mode Any-PHY Slave Notes: *
UTOP_MODE[1:0] ANY-PHY_EN n/a 1
16_BIT_MODE
UTOPIA Level 2 Multi-Address Slave mode is only valid in the AAL1gator-32; for the AAL1gator-8 and AAL1gator-4, UTOP_MODE[1:0] = "11" is Reserved and should not be used. If 16_BIT_MODE is set, then all 16 bits of the UTOPIA data bus or Any-PHY interface are used. If 16_BIT_MODE is low, then only the lower 8 bits are used.
* *
Parity Generation The EVEN_PAR bit determines the calculated parity across data bytes/words sent out of the source interface. EVEN_PAR 0 1 Odd parity Even parity. Function
Chip Select Enable for Any-PHY Mode The CS_MODE_EN bit is used to determine the use of the TPHY_ADDR(3)/TCSB input pin. This bit should only be set in Any-PHY mode. CS_MODE_EN 0 1 Function The TPHY_ADDR(3)/TCSB input pin is used as an address bit (TPHY_ADDR(3)) for the sink side interface. The TPHY_ADDR(3)/TCSB input pin is used as a chip select (TCSB) for the sink side interface.
Slave Sink Address The CFG_ADDR[15:0] bits of the Slave Sink Address Configuration Register (0x80124) contain the configured slave address used for UTOPIA Level 2 and Any-PHY operation in the sink direction. Depending on the mode of the
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UTOPIA/Any-PHY interface different bits of this field are used. See the following table for details. Polling MODE UTOPIA-2 Single-Addr UTOPIA-2 Multi-Addr Any-PHY with CSB PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP [2]=device CFG_ADDR [4:0]=device [4:2]=device Selection PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP CFG_ADDR is prepended Any-PHY without CSB [3:2]=device [1:0]=A1SP [3:2]=device [3:2]=device [1:0]=A1SP CFG_ADDR is prepended [15:2]=device [15:2]=device CFG_ADDR [4:0]=device [4:2]=device
Notes: * In Any-PHY mode, the upper 14 bits of the prepended address are compared with CFG_ADDR[15:2]. The bottom two bits are not compared with this field and are just used to select the target A1SP. If in 8-bit mode CFG_ADDR[7:2] is used instead. In Any-PHY mode, if CS_MODE_EN='0', then CFG_ADDR[4:3] = "00". In Any-PHY mode, if CS_MODE_EN='1', then CFG_ADDR[3]="0".
* * 6.4
VCI Based UTOPIA to UTOPIA Loopback The U2U_LOOP_VCI[15:0] bits in the U2U_LOOP_VCI (0x80125) register specify the VCI to be used for VCI based UI to UI loopback. If VCI_U2U_LOOP is set in the UI_COMN_CFG_REG (0x80120), then any cell received from the UI bus, with a VCI which matches this programmed VCI, will be sent back out to the UI bus. The value of this register should be changed only when VCI_U2U_LOOP is disabled. U2U_LOOP_VCI[15:0] defaults to 0x0000.
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6.4.1 VCI Loopback Setup Example in Multi-Address mode Internal routing circuitry in UTOPIA Level 2 multi-address mode requires some special consideration of the VCI values and select addresses. An example of a proper configuration for VCI based loopback while in UTOPIA Level 2 multi-address mode is shown in Figure 9. Note that cells sent to the sink interface address TxAddr=bbb10 (where bbb is the configured base address) which have VCI[15]=y and VCI[12:0]=z will be looped back because the resulting internal VCI will match that in the U2U_LOOP_VCI (0x80125) register. To maintain correct functionality, the cell's VCI[14:13] should match that of the lower bits of the select address TxAddr, i.e. VCI[14:13]=10, and thus will appear unchanged when exiting the source side. If Shift_VCI= 0 then all requirements on VCI[14:13] are placed on VCI[10:9] instead. All loopback cells will appear at the source side interface, regardless of the setting of source configuration address (UI_SRC_CFG_ADR), but to maintain symmetry the source configuration address should be set to RxAddr=bbb10 in this example so that looped back cells appear on the same source address (Rx slave) port as the sink address (Tx slave). An alternate setting would be to set incoming VCI[14:13] = TxAddr(1:0) = RxAddr(1:0) = "00", thus using the sink side base address as the loopback address.
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Figure 9 - UTOPIA Level 2 Multi-Address Mode with VCI Based Loopback
Cell Data VCI(15) = Y VCI(14:13) = 10 VCI(12:0) = Z RxAddr =BBB10 Cell Data VCI(15) = Y VCI(14:13) = 10 VCI(12:0) = Z
TxAddr =BBB10
Tx select address (1:0) ends up in source side VCI
TDAT_O
TADR_I
RDAT_I
RADR_I
UI_SRC_CFG_ADDR(4:2)=BBB UI_SRC_CFG_ADDR(1:0)=10 UI_SRC_INTF
UI_SNK_CFG_ADDR(4:2)=BBB UI_SNK_CFG_ADDR(1:0)= ignored UI_SNK_INTF
Shift_VCI = 1 U2U_LOOP_VCI(15)= Y U2U_LOOP_VCI(14:13)= 10 U2U_LOOP_VCI(12:0)= Z
AAL1_UI
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7
DATA STRUCTURES Please note that only the memory locations for A1SP 0 are used for the AAL1gator-8, and that only the memory locations for lines 0 through 3 of A1SP 0 are used for the AAL1gator-4.
7.1
Transmit Data Structures Figure 10 shows the format of the Transmit Data Structures block. Figure 10 - Transmit Data Structures Memory Map
00020 0002F 00030 0003F 00040 003FF 00400 0047F 00480 004FF 00500 006FF 00700 007FF 00800 00FFF 01000 013FF 01400 0143F 01440 01FFF 02000 03FFF 04000 07FFF T_SEQNUM_TBL T_ADD_QUEUE Unused T_COND_SIG T_COND_DATA Unused Reserved (Frame Advance FIFO) Reserved (Transmit Calendar) Reserved (Transmit Signaling Buffer) T_OAM_QUEUE Unused T_QUEUE_TBL Reserved (Transmit Data Buffer)
Note the addresses listed below are the offsets within each A1SP address space as described in section 4. Note "A" in the Addr column in Table 3 means A1SP digit: (000x=A1SP0, 011x=A1SP3)
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Table 3 - Transmit Structures Summary Name R/W Org Size Addr Description
P_FILL_CHAR
R/W
1 word
2 bytes
0004H
Reserved(AQ) T_SEQNUM_TBL
R/W R/W
16 words 16 words 32 bytes x 8 lines
32 bytes 32 bytes 256 bytes
0030H - 003FH 0020H - 002FH A 0400H A 047FH 0480H04FFH
The empty bytes in a partially filled cell are filled with P_FILL_CHAR. (Reserved (AQ)) The Transmit Sequence Number Table is initialized according to a table. This table stores the signaling to be used when the TX_COND bit in the T_QUEUE_TBL is set. This table stores the data to be used when the TX_COND bit in the T_QUEUE_TBL is set. Reserved (Frame Advance FIFO). Reserved (Transmit Calendar). Reserved (Transmit Signaling Buffer). The Transmit OAM Queue contains the OAM cells to be transmitted.
T_COND_SIG
R/W
T_COND_DATA
R/W
32 bytes x 8 lines
256 bytes
Reserved Reserved Reserved T_OAM_QUEUE
R/W R/W R/W R/W
256 words 8 x 128 x2 words 8 x 256 bytes 2 x 32 words
512 bytes 4 kBytes 2 kBytes 128 bytes
0700H07FFH 0800H0FFFH 1000H13FFH 1400H143FH
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Name
R/W
Org
Size
Addr
Description
T_QUEUE_TBL
R/W
256 x 32 words
16 kBytes
2000H3FFFH
Reserved Notes:
R/W
8x2K words
32 kBytes
4000H7FFFH
The Transmit Queue Table contains all pointers and variables that are queue-dependent. Reserved (Transmit Data Buffer).
All ports marked as "Reserved" must be initialized to 0 at initial setup. Software modifications to these locations after setup will cause incorrect operation. All read/write port bits marked "Not used" must be written with the value 0 to maintain software compatibility with future versions. All read-only port bits marked "Not used" are driven with a 0 and should be masked off by the software to maintain compatibility with future versions. 7.1.1 P_FILL_CHAR Organization: One word Base address within A1SP: 4H Type: Read/Write Function: Contains the fill character for partially filled cells. Format: Refer to the following table.
Field (Bits) Not used (15:8) P_FILL_CHAR (7:0)
Description Write with a 0 to maintain future software compatibility. Character used in partially filled cells. Initialize to the desired value.
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7.1.2 T_SEQNUM_TBL Organization: 16 words Base address within A1SP: 20H Index: 1H Type: Read/Write Function: Stores all possible first bytes in the payload: CSI, SN, and SNP. This table must be loaded into the SRAM on every power cycling. Initialization: Initialize to the values in the following table
Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Data Value 0000H 0017H 002DH 003AH 004EH 0059H 0063H 0074H 008BH 009CH 00A6H 00B1H 00C5H 00D2H 00E8H 00FFH
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7.1.3 T_COND_SIG Organization: 32 bytes x 8 lines Base address within A1SP: 400H Index: 10H Type: Read/Write Function: Stores the transmit conditioned signaling. Initialization: Initialize to the conditioned signaling value for the channel. This value typically depends on the type of channel unit that is connected. For example, a Foreign Exchange Office (FXO) needs a different conditioning value than a Foreign Exchange Subscriber (FXS). Format: One nibble per byte, two bytes per word, 16 words per line. Refer to the following table.
Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H
Name T_COND_SIG_0 T_COND_SIG_1 T_COND_SIG_2 T_COND_SIG_3 T_COND_SIG_4 T_COND_SIG_5 T_COND_SIG_6 T_COND_SIG_7
Description Transmit conditioned signaling for line 0. Transmit conditioned signaling for line 1. Transmit conditioned signaling for line 2. Transmit conditioned signaling for line 3. Transmit conditioned signaling for line 4. Transmit conditioned signaling for line 5. Transmit conditioned signaling for line 6. Transmit conditioned signaling for line 7.
T_COND_SIG_n Word Format Field (Bits) Not used (15:12) T_COND_SIG_A_H (11) Description Write with a 0 to maintain future software compatibility. Transmit conditioned A bit for: Offset = ((channel -1) / 2) + line x 16.
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Field (Bits) T_COND_SIG_B_H (10) T_COND_SIG_C_H (9) T_COND_SIG_D_H (8) Not used (7:4) T_COND_SIG_A_L (3) T_COND_SIG_B_L (2) T_COND_SIG_C_L (1) T_COND_SIG_D_L (0) 7.1.4 T_COND_DATA
Description Transmit conditioned B bit for: Offset = ((channel -1) / 2) + line x 16. Transmit conditioned C bit or A bit if T1 SF for: Offset = ((channel -1) / 2) + line x 16. Transmit conditioned D bit or B bit if T1 SF for: Offset = ((channel -1) / 2) + line x 16. Write with a 0 to maintain future software compatibility. Transmit conditioned A bit for: Offset = (channel / 2) + line x 16. Transmit conditioned B bit for: Offset = (channel / 2) + line x 16. Transmit conditioned C bit or A bit if T1 SF for: Offset = (channel / 2) + line x 16. Transmit conditioned D bit or B bit if T1 SF for: Offset = (channel / 2) + line x 16.
Organization: 32 bytes x 8 lines Base address within A1SP: 480H Index: 10H Type: Read/Write Function: Stores the transmit conditioned data. Initialization: Initialize to the conditioned data appropriate for the channel, which typically depends on the type of channel connected to the device. For example, data usually needs an FFH value and voice needs a small Pulse Coded Modulation (PCM) value. Format: Two bytes per word, 16 words per line. Refer to the following table.
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Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H
Name T_COND_DATA_0 T_COND_DATA_1 T_COND_DATA_2 T_COND_DATA_3 T_COND_DATA_4 T_COND_DATA_5 T_COND_DATA_6 T_COND_DATA_7
Description Transmit conditioned data for line 0. Transmit conditioned data for line 1. Transmit conditioned data for line 2. Transmit conditioned data for line 3. Transmit conditioned data for line 4. Transmit conditioned data for line 5. Transmit conditioned data for line 6. Transmit conditioned data for line 7.
T_COND_DATA_n Word Format Field (Bits) T_COND_DATA_H (15:8) T_COND_DATA_L (7:0) 7.1.5 RESERVED (Transmit Signaling Buffer) This structure is reserved and need not be initialized to 0. Software modifications to this structure after setup will cause incorrect operation. Organization: Eight multiframes x 32 DS0s x 8 lines. Each of the eight lines are allocated a separate signaling buffer. Each DS0 generates one new nibble of signaling per multiframe. The data is stored in the buffer in the order it is received from the framer device. Different framers provide the signaling information in different formats, as the following illustration shows, for one multiframe worth of signaling data. Base address: 01000H Index: 80H Type: Read/Write Function: Stores the outgoing signaling data. Description Transmit conditioned data offset = ((channel / 2) + 1) + line x 16. Transmit conditioned data offset = (channel / 2) + line x 16.
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Figure 11 - SDF-MF Format of the T_SIGNALING BUFFER
15
Word 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bit 16 18 20 22 24 26 28 30 17 19 21 23 25 27 29 31 0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15
0
The upper nibble of each byte is 0.
7.1.6 T_OAM_QUEUE Organization: 2 cells x 32 words Base address within A1SP: 01400H Index: 20H Type: Read/Write Function: Stores two transmit OAM cells. Initialization: An optimization is to initialize to the body of an OAM cell so only the header must be modified before sending. Format: Refer to the following table.
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Offset 01400H 01420H
Name T_OAM_CELL_1 T_OAM_CELL_2
Description Transmit OAM cell 1. Transmit OAM cell 2.
T_OAM_CELL_n Format Offset Word 0 Word 1 Word 2 Bits 15:8 Header 1 Header 3 Header 5 (HEC) (Pre-calculated by software) Bits 7:0 Header 2 Header 4 Bits 7:1 Bit 0 0 Disables CRC-10 insertion. 1 Enables CRC-10 insertion. Word 3 . . . Word 26 Payload 1 . . . Payload 47 Payload 48 Payload 2 . . . Not used. Set to 0.
If CRC-10 is enabled in Word 2, set data to 0 in Word 26. Word 26 will be replaced by the computed CRC-10 result as the cell is transmitted. Note: Programming the HEC (word 2 of T_OAM_CELL_n) is optional if this is already done in the PHY device that is interconnected to the AAL1gator. 7.1.7 T_QUEUE_TBL Organization: 256 x 32 words Base address within A1SP: 2000H Index: 20H Type: Read/Write
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Function: Configures the VCs. Format: Each queue will be allocated 32 consecutive words. Offset 0H 1H 2H 3H Name Reserved Description (Data pointer.) Initialize to FFFFH each time this queue is initialized. Not used Initialize to `0' each time this queue is initialized to maintain future software compatibility. T_COND_CELL_CNT A 16-bit rollover count of conditioned cells transmitted. T_SUPPRESS_CNT A 16-bit rollover count of cells not sent because of a line resynchronization. Or, if in UDF-HS mode, a 16-bit rollover count of cells not sent because TX_ACTIVE is not set. This counter also counts when cells are not sent because SUPPRESS_TRANSMISSION is set. Not used Initialize to `0' each time this queue is initialized to maintain future software compatibility. Reserved (Sequence number.) Initialize to `0' each time this queue is initialized. QUEUE_CONFIG The configuration of the current queue. Initialize to the proper value. T_CELL_CNT A 16-bit count of the cells transmitted. TX_HEAD(1:2) Header byte 1 in bits 15:8, header byte 2 in bits 7:0. TX_HEAD(3:4) Header byte 3 in bits 15:8, header byte 4 in bits 7:0. TX_HEAD(5) Header byte 5 (pre-calculated HEC) in bits 15:8. QUE_CREDITS A 10-bit quantity representing the number of byte credits accumulated for the queue. CSD_CONFIG Stores the average number of bytes in each cell, and carries the number of DS0s for this queue. Not used Initialize to `0' each time this queue is initialized to maintain future software compatibility. T_CHAN_ALLOC(15: A bit table with a bit set per DS0 allocated to 0) this queue for DS0s 15:0 on the line defined by queue / 32.
4H 5H 6H 7H 8H 9H AH BH CH DH EH
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Offset FH
Name
Description
T_CHAN_ALLOC(31: A bit table with a bit set per DS0 allocated to 16) this queue for DS0s 31:16 on the line defined by queue / 32. 10H T_CHAN_LEFT(15:0 Initialize to the same value as ) T_CHAN_ALLOC(15:0). 11H T_CHAN_LEFT(31:1 Initialize to the same value as 6) T_CHAN_ALLOC(31:16). 12H TRANSMIT_CONFIG Controls transmission of data. 13H Reserved (T_CUR_ACT_CHAN(15:0)) Initialize to 0 each time this queue is initialized. 14H Reserved (T_CUR_ACT_CHAN(31:16)) Initialize to 0 each time this queue is initialized. 15H Reserved (T_NEW_ACT_CHAN(15:0)) Initialize to 0 each time this queue is initialized. 16H Reserved (T_NEW_ACT_CHAN(15:0)) Initialize to 0 each time this queue is initialized. 17H Reserved (CSD_BYTES_LEFT) Only used in DBCES mode. When operating in DBCES mode this register must be initialized to the structure size minus the portion of a structure that fits in the first cell. The formula to calculate this value is: struct_size - ((46-bitmask_size) MOD struct_size) The number of data bytes in the first cell is 47 minus the structure pointer and the bitmask size. The MOD operation determines the number of bytes from the structure that make it into the first cell. This number is then subtracted from the structure size to determine how many bytes are left in the structure after the first cell. 18H-1FH Not used Initialize to 0 each time this queue is initialized. T_COND_CELL_CNT Word Format Initialize to "0000" and at all other times the word is read only. The word maintained by TALP.
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Field (Bits) T_COND_CELL_CNT (15:0)
Description A 16-bit rollover count of conditioned cells transmitted. This counter increments when cells with conditioned data is sent. If only signaling is conditioned this counter will not increment.
T_SUPPRESS_CNT Word Format Initialize to "0000" and at all other times the word is read only. The word is maintained by TALP.
Field (Bits) T_SUPPRESS_CNT (15:0)
Description A 16-bit rollover count of cells not sent because of a line resynchronization. Or, if in UDF-HS mode, a 16-bit rollover count of cells not sent because TX_ACTIVE is not set. This counter also counts when cells are not sent because SUPPRESS_TRANSMISSION is set.
QUEUE_CONFIG Word Format This word is maintained by the microprocessor.
Field (Bits) TX_COND (15)
Description Sends data and signaling from the transmit conditioned data area according to the conditioning mode selected in the TRANSMIT_CONFIG register. Initialize to the proper value.
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Field (Bits) TX_ACTIVE (14)
Description Enables this queue. To enable connections: * * 1)Assert this bit.
2)Add this queue to the ADDQ_FIFO Register. To disable connections, clear the TX_ACTIVE bit. This queue is then removed from the calendar queue the next time a cell would have been sent. Once this bit is cleared, the associated queue must not be returned to the add-queue FIFO until FRAMES_PER_CELL frames have passed by. If quick reconfiguration is required and the size of the queue is not going to change (number of allocated channels), then use SUPPRESS_XMT bit to pause queue and reconfigure instead of clearing TX_ACTIVE bit. When reactivating a previously active queue, be sure to reinitialize all the registers in the queue table for that queue.
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Field (Bits) FRAMES_PER_CELL (13:8)
Description A 6-bit integer specifying the maximum number of frames required to have enough data to construct a cell (round up of BYTE_PER_CELL/number of DS0s assigned) plus 1. For example, for a T1 line in SDF-FR mode with five DS0s, initialize this field to 11. In T1 SDF-MF or SDF-FR modes, the FRAMES_PER_CELL is encoded as the number of 24-frame multiframes required in bit 13 and the number of frames mod 24 in bits 12:8. In all other modes, including unstructured T1 mode, encode this value as the maximum number of 256 bit increments required to create a cell. For unstructured mode with full cells, set this value to 3. * For channels with a single DS0, encode the value 48 as one multiframe and 24 frames. When calculating the FRAMES_PER_CELL value, do not subtract the bytes used by signaling nibbles from the value. For example, for an SDF-MF, single DS0, full cell connection, use the value 47 + 1 = 48 and not 46 + 1 = 47. For SDF-MF connections using partial cells, set FRAMES_PER_CELL to (round up of BYTE_PER_CELL/number of DS0s assigned) plus 2. This prevents scheduling more than one cell per frame.
*
*
T_CHAN_NO_SIG (7)
Set to 1 to send cells with no signaling when in SDF-MF mode. This is the same as using this queue in SDF-FR mode, which means the structure forms on frame boundaries instead of multiframe boundaries. Set to 1 only when sending cells with a single DS0 without a pointer in the SDF-FR mode. To conform to the CES standard V 2.0 when using a single DS0 in SDF-FR mode, no pointer should be used.
T_CHAN_UNSTRUCT (6)
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Field (Bits) BYTES_PER_CELL (5:0)
Description A 6-bit integer specifying how many bytes per cell are required if no structure pointers are used. For UDF_HS mode, this value must be 47. This number must be set so the cell generation rate per queue is slower than once per frame. For unstructured lines, this means between 33 and 47. For structured applications, the BYTES_PER_CELL number must exceed the number of DS0 channels allocated to the queue. For example, a two channel queue may have the number set from 3 to 47. For SDF-MF connections with more than 16 channels allocated, the BYTES_PER_CELL number must exceed the number of DS0 channels allocated to the queue by two. For example, a 17 channel SDF-MF queue may have the number set from 19 to 47. For AAL0 connections this field should be set to 48. This is due to the fact that there is no sequence number byte in AAL0 cells.
T_CELL_CNT Word Format Initialize to "0000" and at all other times the word is read only. The word is maintained by TALP.
Field (Bits) T_CELL_CNT (15:0)
Description A 16-bit count of the data cells transmitted. Rolls to 0 from FFFFH. Initialize to 0. After initialization, do not write to this word.
TX_HEAD(1:2) Word Format This word is maintained by the microprocessor.
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PROGRAMMER'S GUIDE
Field (Bits) TX_HEAD(1) (15:8) TX_HEAD(2) (7:0)
Description First header byte in bits 15:8. Initialize to the proper value. Second header byte in bits 7:0. Initialize to the proper value.
TX_HEAD(3:4) Word Format This word is maintained by the microprocessor.
Field (Bits) TX_HEAD(3) (15:8) TX_HEAD(4) (7:0) TX_HEAD(5) Word Format This word is maintained by the microprocessor.
Description Third header byte in bits 15:8. Initialize to the proper value. Fourth header byte in bits 7:0. Initialize to the proper value.
Field (Bits) TX_HEAD(5) (15:8) Not used (7:0)
Description Fifth header byte that contains the precalculated HEC word. Initialize to the proper value. Write with a 0 to maintain compatibility with future software versions.
Note: Programming the HEC is optional if this is already done in the PHY device that is interconnected to the AAL1gator. QUE_CREDITS Word Format After initialization this word is read only. The word is maintained by CSD.
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PROGRAMMER'S GUIDE
Field (Bits) FRAME_REMAINDER (15:14)
Description A 2-bit quantity representing the remainder of the division operation the CSD performs when converting the frame differential (expressed in frames) to the frame differential (expressed in eighths of multiframes). This quantity is maintained by the CSD. Initialize to 00b. Write with a 0 to maintain compatibility with future software versions. A 10-bit quantity representing the number of byte credits accumulated for the queue. It is measured in eighths (three LSBs are fractional bits). Initialize to 47 x 8 (178H) for UDF modes full cells, 46.875 x 8 (177H) for SDF mode full cells, or to the partially filled cell length x 8. For SDF-MF queues start with (177H) and add 8 times the number of signaling bytes which would occur in the first cell. (For 1 DS0 (E1) this is (187H), for 1 DS0(T1) or 2 DS0s (E1) this is (17FH). For all other configurations the initial value should be (177H).
Not used (13:10) QUEUE_CREDITS (9:0)
CSD_CONFIG Word Format This word is maintained by the microprocessor.
Field (Bits) NUM_CHAN (15:10)
Description A 6-bit integer specifying the number of DS0 channels being carried by this queue. If a queue serves seven DS0s, initialize this field to 7. This field has to be set to 32 in UDF-ML mode. It is not used in UDF-HS mode.
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PROGRAMMER'S GUIDE
Field (Bits) AVG_SUB_VALU (9:0)
Description A 10-bit integer representing the average number of data bytes per cell measured in eighths. The three LSBs represent bits after the fixed decimal point. Initialize to 46.875 (0101110.111) for full cells when in SDF-FR or SDF-MF mode. Initialize to 47 (0101111.000) for full cells when in UDF-ML mode. For partial cells, this value is the same as the partially filled value x 8. This field is not used in UDF-HS mode.
T_CHANNEL_ALLOC(15:0) Word Format This word is maintained by the microprocessor.
Field (Bits) T_CHANNEL_ALLOC (15:0)
Description A bit table with a bit set per DS0 allocated to this queue for DS0s 15 to 0 on the line defined by queue / 32. Initialize to the proper value for SDF-MF and SDF-FR modes and to FFFFH for UDF-ML and UDF-HS modes.
T_CHANNEL_ALLOC(31:16) Word Format This word is maintained by the microprocessor.
Field (Bits) T_CHANNEL_ALLOC (31:16)
Description A bit table with a bit set per DS0 allocated to this queue for DS0s 31 to 16 on the line defined by queue / 32. Initialize to the proper value for SDF-MF and SDF-FR modes and to FFFFH for UDF-ML and UDF-HS modes.
T_CHANNEL_LEFT(15:0) Word Format After initialization this word is read only. The word is maintained by TALP.
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PROGRAMMER'S GUIDE
Field (Bits) T_CHANNEL_LEFT (15:0)
Description Initialize to the same value as T_CHAN_ALLOC(15:0).
T_CHANNEL_LEFT(31:16) Word Format After initialization this word is read only. The word is maintained by TALP.
Field (Bits) T_CHANNEL_LEFT (31:16)
Description Initialize to the same value as T_CHAN_ALLOC(31:16).
TRANSMIT_CONFIG Word Format This word is maintained by the microprocessor.
Field (Bits) SUPPRESS_XMT (15) LOOPBACK_ENABLE (14) AAL0_MODE_ENABLE (13)
Description Set to 1 to suppress the generation of cells for this queue. Cells are scheduled but not transmitted. Set to 1 to loopback cell to receive side. Set VPI/VCI to corresponding receive queue number. Set to 1 to build AAL0 cells instead of AAL1.
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PROGRAMMER'S GUIDE
Field (Bits) COND_MODE (12:11)
Description Selects the conditioning mode with the following encoding: 00 Both signaling and data are conditioned 01 Only signaling is conditioned 10 Only data is conditioned 11 reserved The chosen mode takes effect when the TX_COND bit is set in the QUEUE_CONFIG memory register. If data is conditioned the T_COND_CELL_CNT counter will increment. If only signaling is conditioned the T_CELL_CNT will increment as normal.
DBCES_ENABLE (10) IDLE_DET_ENABLE (9)
Set to 1 to enable DBCES functionality. Set to 1 to enable idle detection in non-DBCES mode. When in this mode a queue which has all idle channels will have its transmission of cells suppressed. Any suppressed cell will cause the T_SUPPRESS_CNT to be incremented. Write with a `0' to maintain future software compatibility.
Not used (8:0)
7.1.8 RESERVED (Transmit Data Buffer) This structure is reserved and must be initialized to 0 at initial setup. Software modifications to this location after setup will cause incorrect operation. Organization: 4 kBytes x 8 lines - Each line is allocated a separate 128 frame buffer memory. For E1 applications, this is large enough to store eight multiframes (32 DS0s x 16 frames x 8 multiframes = 4096 bytes). In T1 mode, 96 frames or four multiframes are stored (24 24 4 = 2880bytes). T1 storage uses 32 bytes per frame and 32 frames per multiframe to simplify address generation. Every data byte is stored in the multiframe line buffers in the order in which it arrives. If E1_with_T1_SIG is set, data is arranged as if in T1 mode. Base address within A1SP: 4000H
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PROGRAMMER'S GUIDE
Index(line): 800H Type: Read/Write Function: Stores the outgoing data. Format: Two data bytes per word, 16 words per frame. T_DATA_BUFFER Word Format Field (Bits) T_DATA_H (15:8) Transmit data for: Channel = (offset mod 16) x 2 + 1. E1 offset = line x 2048 + multiframe x 256 + frame x 16 + (channel - 1) / 2. T1 offset = line x 2048 + multiframe x 512 + frame x 16 + (channel - 1) / 2. T_DATA_L (7:0) Transmit data for: Channel = (offset mod 16) x 2. E1 offset = line x 2048 + multiframe x 256 + frame x 16 + channel / 2. T1 offset = line x 2048 + multiframe x 512 + frame x 16 + channel / 2. 7.2 Receive Data Structures Figure 12 shows the format of the Receive Data Structures block in more detail. Description
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Figure 12 - Receive Data Structures
08000 08001 08002 08003 08004 0801F 08020 0802F 08030 08037 08038 0803F 08040 0807F 08080 080FF 08100 081FF 08200 0827F 08280 083FF 08400 0847F 08480 084FF 08500 087FF 08800 08FFF 09000 09FFF 0A000 0BFFF 0C000 0DFFF 0E000 0FFFF 10000 1FFFF R_OAM_QUEUE_TBL R_OAM_CELL_CNT R_DROPPED_OAM_CELL_CNT Unused Reserved (SRTS Queue Pointers) Unused R_SRTS_CONFIG Unused R_CRC_SYNDROME Unused R_CH_TO_QUEUE_TBL Unused R_COND_SIG R_COND_DATA Unused Reserved (Receive SRTS Queue) Reserved (Receive Signaling Buffer) R_QUEUE_TBL Unused R_OAM_QUEUE Reserved (Receive Data Buffer)
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PROGRAMMER'S GUIDE
Note the addresses listed below are the offsets within each A1SP address space as described in section 4. Name R_OAM_QUEUE_TBL R_OAM_CELL_CNT R_DROP_OAM_CELL Reserved R_SRTS_CONFIG R_CRC_SYNDROME R_CH_TO_QUE_TBL R_COND_SIG R_COND_DATA Reserved Reserved R_QUEUE_TBL R_OAM_QUEUE Reserved Org 2 words 1 word 1 word 16 words 2 bytes x 8 lines 128 words 128 words 16 x 8 bytes 32 x 8 bytes 8 x 256 words 8 x 32 x 16 words 256 x 32 words 256 x 64 bytes 8 x 512 x 32 bytes Size 4 bytes 2 bytes 2 bytes 32 bytes 16 bytes Addr 8000H- 8001H 8002H 8003H 8020H802FH 8038H803FH Description Receive OAM head and tail pointers. Count of received OAM cells. Count of dropped OAM cells. Reserved (SRTS Queue Pointers). Receive SRTS configuration. Mask of bits. Initialized from a table. Receive channel to queue table. Receive signaling conditioning values. Receive data conditioning values. Reserved (Receive SRTS Queue). Reserved (Receive Signaling Buffer). Receive queue table. Receive OAM queue.
256 bytes 8080H80FFH 256 bytes 8200H827FH 256 bytes 8400H847FH 256 bytes 8480H84FFH 4 kBytes 8800H8FFFH 8 kBytes 9000H9FFFH 16 kBytes 16 kBytes 128 kBytes A000HBFFFH E000HFFFFH
10000H- Reserved (Receive 1FFFFH Data Buffer).
This section describes the structures used by the receive side of the AAL1gator.
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PROGRAMMER'S GUIDE
Notes: * All ports marked as "Reserved" must be initialized to 0 at initial setup. Software modifications to these locations after setup will cause incorrect operation. All read/write port bits marked "Not used" must be written with the value 0 to maintain software compatibility with future versions. All read-only port bits marked "Not used" are driven with a 0 and should be masked off by the software to maintain compatibility with future versions.
* *
7.2.1 R_OAM_QUEUE_TBL Organization: 2 words Base address within A1SP: 8000H Index: 1H Type: Read/Write Function: OAM cells received from the ATM side are stored in a FIFO queue in the memory. Head and tail pointers are used to keep track of the read and write locations of the OAM cell buffers. There are 256 cell buffers in the OAM receive queue. Of these 256 cell buffers, 255 are usable. The 256th buffer is used to detect a full queue as follows: When the queue is empty, OAM_HEAD = OAM_TAIL = N. When a cell is received, the cell is written into the buffer at index (OAM_TAIL + 1) mod 256, and OAM_TAIL is replaced with (OAM_TAIL + 1) mod 256. When the processor receives an interrupt, it reads the cell at the buffer index (OAM_HEAD + 1) mod 256. After completing the read, it sets OAM_HEAD to (OAM_HEAD + 1) mod 256. This process is continued until OAM_HEAD = OAM_TAIL, at which time the OAM receive queue is empty. The receive OAM interrupt can be cleared by asserting the CLR_RX_OAM_LATCH bit in the CMD_REG. If an OAM cell arrived between the time the OAM_TAIL was last read and CLR_RX_OAM_LATCH was asserted, this OAM cell's arrival can be detected within the interrupt service routine by re-reading OAM_TAIL after CLR_RX_OAM_LATCH was asserted.
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PROGRAMMER'S GUIDE
OAM Queue Format Offset 0 1 Name OAM_HEAD OAM_TAIL Head pointer Tail pointer Description
OAM_HEAD Word Format Field(Bits) OAM_HEAD (7:0) OAM_TAIL Word Format Field(Bits) OAM_TAIL (7:0) 7.2.2 R_OAM_CELL_CNT Organization: 1 word Base address within A1SP: 8002H Index: 1H Type: Read/Write Function: 16-bit rollover counter that counts the number of OAM cells received. The software must initialize this counter to 0 during reset. R_OAM_CELL_CNT Word Format Field(Bits) R_OAM_CELL_CNT (15:0) Description 16-bit rollover counter that counts the number of OAM cells received. The software must initialize this counter to 0 during reset. After initialization, do not write to this word. Description Incremented by the RALP after it writes a cell to the OAM cell queue. Initialize to 0. Description The microprocessor should increment to the next cell location when it reads a cell. Initialize to 0.
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PROGRAMMER'S GUIDE
7.2.3 R_DROP_OAM_CELL Organization: 1 word Base address within A1SP: 8003H Index: 1H Type: Read/Write Function: 16-bit rollover counter that counts the number of dropped OAM cells. The software should initialize this counter to 0 during reset. R_DROP_OAM_CELL Word Format Field(Bits) R_DROP_OAM_CELL (15:0) Description 16-bit rollover counter that counts the number of OAM cells dropped. OAM cells are dropped when more than 255 are present in the receive queue. The software must initialize this counter to 0 during reset. After initialization, do not write to this word.
7.2.4 R_SRTS_CONFIG Organization: 2 bytes x 8 lines Base address within A1SP: 8038H Index: 1H Type: Read/Write Function: This table stores the CDVT for the SRTS channel, expressed in the number of queued SRTS nibbles. Initialization: Initialize to the number of SRTS nibbles equivalent to the CDVT for the data by rounding up. Each frame of CDVT for unstructured applications represent 256 bits. Each SRTS nibble represents 3008 bits, which is the number of data bits in eight cells. Therefore, the number of SRTS nibbles that corresponds to the CDVT can be determined by dividing the CDVT number in frames by 3008 / 256, or 11.75, and rounding up to the next higher integer. Format: One byte per line. Refer to the following table.
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R_SRTS_CONFIG Format Offset 0h 1h 2h 3h 4h 5h 6h 7h Name R_SRTS_CDVT_0 R_SRTS_CDVT_1 R_SRTS_CDVT_2 R_SRTS_CDVT_3 R_SRTS_CDVT_4 R_SRTS_CDVT_5 R_SRTS_CDVT_6 R_SRTS_CDVT_7 Description Receive SRTS CDVT for line 0 Receive SRTS CDVT for line 1 Receive SRTS CDVT for line 2 Receive SRTS CDVT for line 3 Receive SRTS CDVT for line 4 Receive SRTS CDVT for line 5 Receive SRTS CDVT for line 6 Receive SRTS CDVT for line 7
R_SRTS_CDVT_n Word Format Field(Bits) Not used (15:5) R_SRTS_CDVT (4:0) 7.2.5 R_CRC_SYNDROME Organization: 128 words Base address within A1SP: 8080H Index: 1H Type: Read/Write Function: This table identifies which bit of the SN/SNP byte has been corrupted, if any. Load after each power cycle. Used internally to perform CRC correction. Description Write with 0 to maintain compatibility with future software versions. Receive SRTS CDVT
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PROGRAMMER'S GUIDE
R_CRC_SYNDROME Word Format Field(Bits) Not used (15:5) RX_CRC_SYNDROME (4:0) Figure 13 - R_CRC_SYNDROME Mask Bit Table Legend
LEGEND 00 01 02 04 08 10 No errors Correct bit 0 Correct bit 1 Correct bit 2 Correct bit 3 SNP error (no need to correct SN field)
Description Write with 0 to maintain compatibility with future software versions. Mask of bits to change.
Table 4 - R_CRC_SYNDROME Mask Bit Table Sequence Number 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset 00 01 02 03 04 05 06 07 08 09 0A 0B 0C Data (Hex) 00 10 10 01 10 08 02 04 01 10 10 00 04 Sequence Number 4 4 4 4 4 4 4 4 4 4 4 4 4 Offset 40 41 42 43 44 45 46 47 48 49 4A 4B 4C Data (Hex) 08 10 04 02 10 00 01 10 02 04 10 08 10
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Sequence Number 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2
Offset 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28
Data (Hex) 02 08 10 02 04 10 08 10 01 00 10 08 10 04 02 10 00 01 10 04 02 08 10 01 10 10 00 10
Sequence Number 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6
Offset 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68
Data (Hex) 01 00 10 01 10 10 00 04 02 08 10 00 10 10 01 10 08 02 04 10 01 00 10 02 04 10 08 10
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Sequence Number 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Offset 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Data (Hex) 08 02 04 00 10 10 01 10 00 01 10 08 10 04 02 10 01 0 10 02 04 10 08
Sequence Number 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Offset 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
Data (Hex) 00 01 10 08 10 04 02 10 08 02 04 00 10 10 01 04 02 08 10 01 10 10 00
7.2.6 R_CH_TO_QUEUE_TBL Organization: 128 words (8 lines x 32 DS0s) Base address within A1SP: 8200H Index: 1H
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Type: Read/Write Hardware Reset Value: 8080H Function: This table associates the DS0 with the queue. It allows the transmit line interface to determine the status of the receive queue supplying bytes for the DS0s being processed. This table is located inside the chip and all time slots are initialized to play out conditioned data. The AAL1gator processes two bytes at a time so the values in the following table are in pairs. For unstructured, low speed lines, set all of the queue values to the receive queue number mod 32. In UDFHS mode, this table is not used. When this queue is in underrun, the AAL1gator reads data for the line from the first word of the R_COND_DATA_0 table. Format: Refer to the following table. R_CH_TO_QUEUE_TBL Format Offset N Name R_CH_TO_QUEUE Description Queue numbers and condition bits associated with this pair of channels where: Line = N / 16. Low channel = (N mod 16) x 2. High channel = (N mod 16) x 2 + 1.
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PROGRAMMER'S GUIDE
R_CH_TO_QUEUE Word Format Field(Bits) RX_COND_H (15:14) Description Determines the type of data to be played out: Options "00", "01", and "11" are executed only when the queue is in an underrun or resume state. 00b When the queue is in underrun, freeze signaling and read the data for this channel from the R_COND_DATA table. 01b When the queue is in underrun, freeze signaling and play out pseudorandom data, which is inserted data from R_COND_DATA, with the MSB controlled by the pseudorandom number algorithm x18 + x7 + 1 (not valid for UDF-HS). 10b Read signaling for this channel from the R_COND_SIG table and the data for this channel from the R_COND_DATA table. 11b When the queue is in underrun freeze signaling and play out the contents of the buffer. RX_SIG_COND_H (13) Overrides the normal signaling with Conditioned signaling 0b Read signaling as indicated by RX_COND_H
Always read signaling for this channel from 1b the R_COND_SIG table QUEUE_H (12:8) Five LSBs of the queue index associated with this DS0. The three MSBs are implicitly those of the line number. Offset = (channel - 1) / 2 + line x 16. For unstructured lines, set to the receive queue number mod 32.
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Field(Bits) RX_COND_L (7:6)
Description Determines the type of data to be played out: Options "00", "01", and "11" are executed only when the queue is in an underrun or resume state. 00b When the queue is in underrun, freeze signaling and read the data for this channel from the R_COND_DATA table. 01b When the queue is in underrun, freeze signaling and play out pseudorandom data, which is inserted data from R_COND_DATA, with the MSB controlled by the pseudorandom number algorithm 18 7 x + x + 1 (not valid for UDF-HS). 10b Read signaling for this channel from the R_COND_SIG table and the data for this channel from the R_COND_DATA table. 11b When the queue is in underrun, freeze signaling and play out the contents of the buffer.
RX_SIG_COND_L (5)
Overrides the normal signaling with Conditioned signaling 0b Read signaling as indicated by RX_COND_L 1b Always read signaling for this channel from the R_COND_SIG table
QUEUE_L (4:0)
Five LSBs of the queue index associated with this DS0. The three MSBs are implicitly those of the line number. Offset = channel / 2 + line x 16.
7.2.7 R_COND_SIG Organization: 16 words x 8 Base address within A1SP: 8400H Index: 10H Type: Read/Write Function: This table stores the signaling to be used when RX_SIG_COND_H or RX_SIG_COND_L equals `1' in the R_CH_TO_QUEUE_TBL.
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PROGRAMMER'S GUIDE
Initialization: Initialize to the conditioned signaling value for the channel. This value typically depends on the type of channel unit that is connected. For example, an FXO channel unit needs a different conditioning value than an FXS channel unit. Format: One nibble per byte, two bytes per word, 16 words per line. Refer to the following table. R_COND_SIG Format Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H Name R_COND_SIG_0 R_COND_SIG_1 R_COND_SIG_2 R_COND_SIG_3 R_COND_SIG_4 R_COND_SIG_5 R_COND_SIG_6 R_COND_SIG_7 Description Receive conditioned signaling for line 0. Receive conditioned signaling for line 1. Receive conditioned signaling for line 2. Receive conditioned signaling for line 3. Receive conditioned signaling for line 4. Receive conditioned signaling for line 5. Receive conditioned signaling for line 6. Receive conditioned signaling for line 7.
R_COND_SIG_n Word Format Field (Bits) Not used (15:12) R_COND_A_H (11) R_COND_B_H (10) R_COND_C_H (9) R_COND_D_H (8) Description Write with a `0' to maintain future software compatibility. Receive conditioned A signaling bit for: Offset = (channel - 1) / 2 + line x 16. Receive conditioned B signaling bit for: Offset = (channel - 1) / 2 + line x 16. Receive conditioned C signaling bit or A bit if T1 SF for: Offset = (channel - 1) / 2 + line x 16. Receive conditioned D signaling bit or B bit if T1 SF for: Offset = (channel - 1) / 2 + line x 16.
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Field (Bits) Not used (7:4) R_COND_A_L (3) R_COND_B_L (2) R_COND_C_L (1) R_COND_D_L (0) 7.2.8 R_COND_DATA Organization: 16 words x 8 Base address within A1SP: 8480H Index: 10H Type: Read/Write
Description Write with a 0 to maintain future software compatibility. Receive conditioned A signaling bit for: Offset = (channel / 2) + line x 16. Receive conditioned B signaling bit for: Offset = (channel / 2) + line x 16. Receive conditioned C signaling bit or A bit if T1 SF for: Offset = (channel / 2) + line x 16. Receive conditioned D signaling bit or B bit if T1 SF for: Offset = (channel / 2) + line x 16.
Function: This table stores the data to be used when RX_COND in the R_CH_TO_QUEUE_TBL equals 00b, 01b, or 10b. Initialization: Initialize to the conditioned data appropriate for the channel. This typically depends on the type of channel connected to the device. For example, data usually needs an FFH value and voice needs a small PCM value. Format: Two bytes per word, 16 words per line. Refer to the following table. R_COND_DATA Format Offset 00000H 00010H Name R_COND_DATA_0 R_COND_DATA_1 Description Receive conditioned data for line 0. Receive conditioned data for line 1.
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Offset 00020H 00030H 00040H 00050H 00060H 00070H
Name R_COND_DATA_2 R_COND_DATA_3 R_COND_DATA_4 R_COND_DATA_5 R_COND_DATA_6 R_COND_DATA_7
Description Receive conditioned data for line 2. Receive conditioned data for line 3. Receive conditioned data for line 4. Receive conditioned data for line 5. Receive conditioned data for line 6. Receive conditioned data for line 7.
R_COND_DATA_n Word Format Field (Bits) R_COND_DATA_H (15:8) R_COND_DATA_L (7:0) Description Receive conditioned data for: Offset = (channel - 1) / 2 + line x 16. Receive conditioned data for: Offset = channel / 2 + line x 16.
7.2.9 RESERVED (Receive SRTS Queue) This structure is reserved. Software modifications to this structure after setup will cause incorrect operation. Organization: 64 words x 8 lines. Each line is allocated a separate 64-entry queue to store the SRTS receive nibbles. Base address within A1SP: 8800H Index: 100H Type: Read/Write Function: The receive signaling queue stores the SRTS bits received from the UTOPIA interface. Initialization: It is not necessary to initialize this structure. Format: One SRTS nibble per word.
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R_SRTS_QUEUE_n Word Format Field (Bits) Not used (15:8) R_SRTS_VAL (7:4) Description Write with a 0 to maintain future software compatibility. Indicates if each SRTS bit contains valid data. When an error occurs which causes a bit to be lost the corresponding bit will be written with a `0'. Each time a new entry is written, the remaining bits which haven't been received yet will also be written with a `0'. So normally this field will be written with a "1000" for the first bit then "1100" for the second bit, then "1110" for the third bit and finally "1111" for the last bit. Receive SRTS data for line = offset / 64.
R_SRTS (3:0)
7.2.10 RESERVED (Receive Signaling Buffer) This structure is reserved. Software modifications to this structure after setup will cause incorrect operation. Organization: 32 x 32 DS0s x 8 lines. Each line is allocated a separate 32 x 32 byte memory. For E1, this allows storage of signaling information for 32 multiframes, unless E1_WITH_T1_SIG is set. T1 applications use only the first 24 bytes of every 32 to store signaling data. In addition, since the transmit data buffer is only 16 multiframes in size, this structure also needs to store only 16 multiframes. Successive multiframes are stored in every other 32-byte buffer. When signaling is frozen due to an underrun, the value in multiframe 0 is used. Base address within A1SP: 9000H Index (line): 200H Type: Read/Write Function: The receive signaling queue stores the signaling that is received from the UTOPIA interface. Initialization: The signaling buffer should be initialized to "0". Also, if R_CHAN_NO_SIG is set for some queues and a specific signaling value is desired to be driven for these queues, then the DS0s in those queues must be initialized to the desired value for all multiframes.
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Format: Two signaling nibbles per word. R_SIG_BUFFER_n Word Format Field (Bits) Not used (15:13) R_SIG_INVALID (12) R_SIG_H (11:8) Description Write with a 0 to maintain future software compatibility. Indicates that the stored signaling is invalid. If signaling is not valid due to lost cells, signaling will freeze. Receive signaling data for: Channel = (offset mod 16) x 2 + 1. Multiframe = (offset mod 512) / 16. Line = offset / 512. Offset = line x 512 + multiframe x 16 + (channel - 1) / 2. Not used (7:5) R_SIG_INVALID (4) R_SIG_L (3:0) Write with a 0 to maintain future software compatibility. Indicates that the stored signaling is invalid. If signaling is not valid due to lost cells, signaling will freeze. Receive signaling data for: Channel = (offset mod 16) x 2. Multiframe = (offset mod 512) / 16. Line = offset / 512. Offset = line x 512 + multiframe x 16 + channel / 2. 7.2.11 R_QUEUE_TBL Organization: 256 x 32 words Base address within A1SP: A000H Index: 20H Type: Read/Write
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Function: Receive Queue Table contains all the structures and pointers specific to a queue. The RALP and RFTC blocks both use the R_QUEUE_TBL. Some of the words are read by both the blocks but written by only one of the blocks. Format: Each queue is allocated 32 consecutive words. Each word is 16-bits wide. The organization of the words is as follows. Table 5 - R_QUEUE_TBL Format Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 10H 11H 12H 13H Name R_STATE_0 R_MP_CONFIG R_STATE_1 R_LINE_STATE R_MAX_BUF R_SEQUENCE_ERR R_INCORRECT_SNP R_CELL_CNT R_ERROR_STKY R_TOT_SIZE R_DATA_LAST R_TOT_LEFT Not used R_SN_CONFIG R_CHAN_ALLOC (15:0) R_CHAN_ALLOC (31:16) Reserved (CHNLEFTL) Reserved (CHNLEFTH) R_DROPPED_CELLS R_UNDERRUNS Description Cell receiver state 0. Bytes per cell and CDVT constant. Cell receiver state 1. Line state. Receive maximum buffer size. 16-bit rollover count of SN errors. 16-bit rollover count of cells with incorrect SNP. 16-bit rollover count of played out cells. Receive sticky bits. Total bytes in structure. Number of signaling bytes in structure. Number of bytes remaining in the structure. Initialize to 0 each time this queue is initialized. Initialize to 0 each time this queue is initialized. Configures sequence number processing algorithm. A bit table with a bit set per DS0 allocated to this queue for DS0s 15 to 0 on the line defined by queue / 32. A bit table with a bit set per DS0 allocated to this queue for DS0s 31 to 16 on the line defined by queue / 32. Initialize to 0 each time this queue is initialized. Initialize to 0 each time this queue is initialized. 16-bit rollover count of cells that were received but dropped. Initialize to 0. 16-bit rollover count of the occurrences of underrun on this queue. Initialize to 0.
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Offset 14H
Name R_LOST_CELLS
Description
16-bit rollover count of the number of lost cells for this queue. Initialize to 0. 15H R_OVERRUNS 16-bit rollover count of the occurrences of overrun on this queue. Initialize to 0. 16H R_PTR_REFRAMES 16-bit rollover count of the occurrences of pointer reframes. Initialize to 0. 17H R_PTR_PAR_ERR 16-bit rollover count of the occurrences of pointer parity errors. Initialize to 0. 18H R_MISINSERTED 16-bit rollover count of the occurrences of misinserted cells. Initialize to 0. 19H R_ROBUST_SN Write pointer for robust SN processing 1AH Reserved (CHNACTL) Initialize to 0 each time this queue is initialized. 1BH Reserved (CHNACTH) Initialize to 0 each time this queue is initialized. 1CH R_RD_PTR_LAST Read pointer for bit integrity through underrun 1DHNot used Initialize to 0 each time this queue is 1FH initialized. All of these locations must be initialized whenever the queue is initialized.
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R_STATE_0 Word Format This word is read-only and is maintained by the RALP
Field (Bits) R_DBCES_BM_IN_NXT (15) R_STRUCT_FOUND (14)
Description Indicates that a Bit Mask will be present in the next structure. Used when a ptr is found that locates the structure in the next cell. Indicates that the receiver structure was found. Initialize to 0.
Reservd(OLDUNDRN_N) Initialize to 0 to maintain future software compatibility. (13) Reservd(UNDRN_2AGO) Initialize to 0 to maintain future software compatibility. (12) Reserved(ACTSN) (11:9) SN_STATE (8:6) 2ND_LAST_SN (5:3) LAST_SN (2:0) Initialize to 0 to maintain future software compatibility. Specifies the state of the SN state machine. Initialize to 0. Specifies the SN that was received two cells ago. Initialize to 0. Specifies the last SN that was received. Initialize to 0.
R_MP_CONFIG Word Format This word is maintained by the microprocessor.
Field (Bits) R_CHK_PARITY (15)
Description If set, check the parity on the incoming structure pointer.
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Field (Bits) R_BYTES_CELL (14:9)
Description A 6-bit integer specifying how many bytes per cell are required if no structure pointers are used. For UDF-HS mode, this must be set to 47. In other modes, set this to the partially filled length. If cells are not partially filled, set this to 47. If set, treats this queue as an AAL0 queue and will write all 48 bytes of payload into the allocated time slots. Receive Cell Delay Variation Tolerance (R_CDVT) is a constant and is programmed by the microprocessor during initialization. It is used by the RFTC after the receipt of the first cell after an underrun. In T1 SDF-MF, E1_WITH_T1_SIG, or SDF-FR mode, the R_CDVT is expressed as the number of multiframes in bits 7:5 and the number of frames in bits 4:0. In E1 and all other T1 modes, R_CDVT is the number of frames. In unstructured applications, the number of frames refers to the number of 256-bit increments. For T1 unstructured modes, this is equivalent to the number of 165.8 ms periods. For Robust SN Processing, this field represents the CDVT desired plus the number of frames stored in the cell that is conditionally stored
R_AAL0_MODE (8) R_CDVT (7:0)
R_STATE_1 Word Format This word is read-only and is maintained by the RALP. This register is located inside the chip and is reset to "0000".
Field (Bits)
Description
Reserved (FRC_UNDRN) Initialize to 0 to maintain future software compatibility. (15) Reserved (SNCRCST) (14) Reserved (PTRMMST) (13) Initialize to 0 to maintain future software compatibility. Initialize to 0 to maintain future software compatibility.
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Field (Bits) Reserved (FNDPTR) (12) Reserved (FNDFRSTPTR) (11) Reserved (DBCES_EN) (10) Not used (9) R_WRITE_PTR (8:0)
Description Initialize to 0 to maintain future software compatibility. Initialize to 0 to maintain future software compatibility. Initialize to 0 to maintain future software compatibility. Driven with a 0. Mask on reads to maintain future software compatibility. Pointer to the frame to which the cell receiver is writing the last accepted cell.
R_LINE_STATE Word Format This word is read-only after initialization and is maintained by the RALP and RFTC. This register is located inside the chip and is reset to 9000H.
Field (Bits) R_UNDERRUN (15) R_RESUME (14) R_SIG_RESUME (13) R_LONG_UNDERRUN (12) Reserved (11:9) R_END_UNDERRUN_P TR (8:0)
Description Indicates that this queue is currently in underrun. Initialize to 1. Indicates that this queue is currently in resume state. Initialize to 0. Indicates that this queue is currently in signal resume state. Initialize to 0. Indicates that the rd_ptr has wrapped while the queue was in underrun Initialize to 0 to maintain future software compatibility. Location read pointer needs to reach after an underrun to begin playing out new data. Initialize to 0 to maintain future software compatibility.
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R_MAX_BUF Word Format This word is maintained by the microprocessor
Field (Bits) R_CHAN_UNSTRUCT (15)
Description Set to 1 only when receiving cells with a single DS0 without a pointer in the SDF-FR mode. This bit is valid only in SDF-FR mode. To conform to the CES standard V 2.0 when using a single DS0 in SDF-FR mode, no pointer should be used. Set to 1 to receive cells without signaling when the line is in SDF-MF mode. This is the same as using this queue in SDF-FR mode, which means that the structure forms on frame boundaries instead of multiframe boundaries. The R_SIG_BUFFER will never be updated for this queue. However, the TL_SIG output will drive the value that was initialized into this timeslot in T_SIG_BUFFER. Set to 1 to drop all cells for this queue. Set to 0 for normal operation. Cells dropped because of this bit are recorded in the ALLOC_TBL_BLANK sticky bit. Set to 1 to maintain bit integrity through underrun. Set to 0 for normal operation. Size in bytes-1 of the DBCES bit mask field. Set to 1 to enable DBCES. This bit is only valid in SDF_FR or SDF MF mode.
R_CHAN_NO_SIG (14)
R_CHAN_DISABLE (13) BITI_UNDERRUN (12) DBCES_BIT_MASK (11:10) DBCES_EN (9)
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Field (Bits) R_MAX_BUF (8:0)
Description Receiver maximum buffer size. The R_MAX_BUF is coded as the number of frames. In all structured modes, this is the number of frames. In all unstructured modes, this is the number of 256-bit increments. If the amount of data in the receive buffer exceeds R_MAX_BUF, no more data will be written, an overflow will be reported, and the queue will be forced into underrun. The maximum value of R_MAX_BUF is 1FEH for most cases. For T1 structured mode or E1 with T1 signaling, the maximum value is 17EH because not all frames are used.
R_SEQUENCE ERROR Word Format This word is read-only and is maintained by the RALP Field (Bits) R_SEQUENCE_ERR (15:0) Description 16-bit rollover count of SN errors. This counter counts transitions from the SYNC state to the OUT_OF_SEQUENCE state. This is the atmfCESAal1SeqErrors count from the CES specification. Note that if SN processing is disabled, this counter will count all out-of-sequence cells. Initialize to 0. Once initialized, do not write to this word. R_INCORRECT_SNP Word Format This word is read-only and is maintained by the RALP Field (Bits) R_INCORRECT_SNP (15:0) Description 16-bit rollover count of cells with SNP errors. This is the atmfCESHdrErrors counter from the CES specification. Initialize to 0. Once initialized, do not write to this word.
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R_CELL_CNT Word Format This word is read-only and is maintained by the RALP Field (Bits) R_CELL_CNT (15:0) Description 16-bit rollover count of received cells. This is the atmfCESReassCells counter from the CES specification. Initialize to 0. Once initialized, do not write to this word.
R_ERROR_STKY Word Format Receive sticky bits should be used for statistics gathering purposes only as there is no means of clearing them without the possibility of missing an occurrence. Initialize to 0.
Field (Bits) TRANSFER (15)
Description This bit is read then written with the same value each time the AAL1gator receives a cell. This feature allows the processor to determine if the AAL1gator was in the middle of a read then write cycle when the processor cleared the other sticky bits. To accomplish this each time the processor wants to clear sticky bits, it should complement this bit. Then, if an additional read of this bit showed it to be the wrong value, then the AAL1gator has had its sticky word update interrupted. A cell was received. There was a parity error in the DBCES Bit Mask.
CELL_RECEIVED (14) DBCES_BIT_MASK_ER R (13)
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Field (Bits) PTR_RULE_ERROR (12)
Description There was a violation of a pointer generation rule. A sequence begins with a cell with SN=0 and ends with a cell with SN=7. This condition will be set if no pointer was received, more than 1 pointer was received or an `out of bounds' pointer was received in the sequence. This condition will only be checked in modes where a pointer is expected and no sequence number error or underrun occurred. A cell was dropped because of a blank allocation table or because R_CHAN_DISABLE (refer to "R_MAX_BUF Word Format" on page144) was asserted. A cell was dropped because a valid pointer has not yet been found. A cell was dropped because a forced underrun condition exists. A forced underrun condition can be caused by overruns and pointer mismatches. A cell was dropped in accordance with the SN Algorithm (as specified in ITU-T Recommendation I.363.1). If Fast SN processing is used this bit will always be set for the first cell if NO_DROP_IN_STAT = 0. A pointer was received. A cell was received with a pointer parity error. An SRTS resume has occurred. A valid SRTS value was received and stored in the SRTS FIFO. A cell was received while the SRTS queue was in underrun. A resume has occurred: a valid cell was received and stored into the buffer. This cell will be played out after 1 CDVT. A cell was dropped because of a pointer mismatch. This event causes a forced underrun condition.
ALLOC_TBL_BLANK (11) POINTER_SEARCH (10) FORCED_UNDERRUN (9) SN_CELL_DROP (8)
POINTER_RECEIVED (7) PTR_PARITY_ERR (6) SRTS_RESUME (5) SRTS_UNDERRUN (4) RESUME (3) PTR_MISMATCH (2)
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Field (Bits) OVERRUN (1) UNDERRUN (0) R_TOT_SIZE Word Format This word is maintained by the microprocessor
Description A cell was dropped due to overrun. The receive buffer exceeded the maximum allowed depth. This event causes a forced underrun condition. A cell was received while the queue was in underrun.
Field (Bits) FRAMES_PER_CELL (15:10) R_TOT_SIZE (9:0)
Description Average number of frames contained within a single cell. This field is not used in UDF-ML or UDF-HS mode. Total bytes minus one in the structure (for example, for an E1 MF VC with two DS0s, R_TOT_SIZE is set to 32). This field is not used in UDF-ML or UDFHS mode. Three formulas for R_TOT_SIZE are: For T1/E1 SDF-FR: R_TOT_SIZE = no. of DS0s - 1 For T1 SDF-MF: R_TOT_SIZE =
(no. of DS0s + 1 ) -- -- -- -- -- -- -- -- ---- --( 24 x no. of DS0s ) + - -- -- -- -- -- -- -- -- - -- - - 1 2
For E1 SDF-MF: R_TOT_SIZE = R_DATA_LAST Word Format This word is maintained by the microprocessor
DS0s + 1 ) (no.--of -- -- -- -- -- -- --- -- -( 16 x no. of DS0s ) + - -- -- -- -- -- -- -- -- -- --- - 1 2
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Field (Bits) Not used (15:13) LAST_CHAN (12:8)
Description Write with a 0 to maintain future software compatibility. Channel number (0 to 31) of the last DS0 with a bit set in the R_CHAN_ALLOC bit table (refer to "R_CHAN_ALLOC(15:0) Word Format" and "R_CHAN_ALLOC(31:16) Word Format" on page153). Write with a 0 to maintain future software compatibility. Write with a 0 to maintain future software compatibility. Number of signaling bytes minus one in the structure (for example, for an E1 SDF-MF VC with six DS0s, R_DATA_LAST is set to 2). An E1-SDFMF VC with seven DS0s is set to 3 as one signaling nibble is unused. Not used in UDF-ML or UDF-HS mode.
R_DATA_LAST = ( no.----------------------------- - 1 --------- of-DS0s + 1)---2
Not used (7:6) Reserved (5:4) R_DATA_LAST (3:0)
R_TOT_LEFT Word Format This word is read-only and is maintained by RALP Field (Bits) Not used (15:13) R_DBCES_BM_LEFT (12:11) R_DBCES_BM_ACT (10) R_TOT_LEFT (9:0) Description Driven with a 0. Mask on reads to maintain future software compatibility. Total unprocessed bytes remaining in bit mask structure. Activity detected in the Bit Mask. Used to indicated whether any channels in the DBCES structure are active or not. Total bytes minus one remaining in the structure. Not used in UDF-ML or UDF-HS mode.
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R_SN_CONFIG Word Format This word is maintained by the microprocessor
Field (Bits) R_CONDQ_DATA (15:8) ROBUST_SN_EN (7) INSERT_DATA (6:5)
Description Value of conditioned data inserted into lost cells depending on the value of INSERT_DATA. Set to 1 to enable the "Robust SN algorithm". Set to a "0' for the "Fast SN Algorithm". Controls the format of the data inserted for lost cells: 00b 01b 10b Insert AIS Insert data from R_CONDQ_DATA. Insert old data from receive buffer.
11b Insert data from R_CONDQ_DATA with the MSB controlled by the pseudorandom number 18 7 algorithm x + x + 1 (not valid for UDF-HS). DISABLE_SN (4) NODROP_IN_START (3) If set, sequence number processing is disabled. Statistics will still be kept but no cells will be dropped due to SN errors. In the "Fast SN Algorithm" for SN processing, the first cell received will always be dropped because a sequence has not been established yet. This bit disables the automatic dropping of cells while in the START state 0 When SN_STATE equals 000b any received cell will be dropped. 1 When SN_STATE equals 000b any received cell with valid SNP will be accepted. MAX_INSERT (2:0) The maximum number of cells that will be inserted when cells are lost. If the number of cells lost exceeds MAX_INSERT, then the queue will be forced into underrun. If this value is set to 000b, it is interpreted the same as 111b, which means that up to seven cells will be inserted.
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R_CHAN_ALLOC(15:0) Word Format This word is maintained by the microprocessor Field (Bits) R_CHAN_ALLOC (15:0) Description A bit table with a bit set per DS0 allocated to this queue for DS0s 15 to 0 on the line defined by queue /32. In UDF-ML and UDF-HS modes, initialize to FFFFH. (DS0 15 is in bit 15).
R_CHAN_ALLOC(31:16) Word Format This word is maintained by the microprocessor Field (Bits) R_CHAN_ALLOC (31:16) Description A bit table with a bit set per DS0 allocated to this queue for DS0s 31 to 16 on the line defined by queue /32. In UDF-ML and UDF-HS modes, initialize to FFFFH. (DS0 31 is in bit 15).
R_DROPPED_CELLS Word Format This word is read-only and is maintained by the RALP R_DROPPED_CELLS 16-bit rollover count Descriptionnon-OAM cells. of dropped Field (Bits) Initialize to 0. Once initialized, do not write to this (15:0) word. Cells may be dropped due to: * * * * * Pointer mismatch. Overrun. Blank allocation table SN processing. Structured cell received while in underrun but structure start has not been found yet.
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R_UNDERRUNS Word Format This word is read-only and is maintained by the RALP Field (Bits) R_UNDERRUNS (15:0) Description 16-bit rollover count of the occurrences of an underrun on this queue. This is the atmfCESBufUnderflows counter. Initialize to 0. Once initialized, do not write to this word. Underruns are counted by the RALP, which does not know an underrun occurred until a cell is received while in underrun. To ensure the underrun count is correct, the counter is not incremented until the queue exits the underrun state and enters the resume state underrun condition. To determine if the queue is in underrun, check the level of the R_UNDERRUN bit in R_LINE_STATE register. If this bit is set, then increment the underrun count by one to get the current count.
R_LOST_CELLS Word Format This word is read-only and is maintained by the RALP Field (Bits) R_LOST_CELLS (15:0) Description 16-bit rollover count of cells that were detected as lost. This is the atmfCESLostCells counter in the CES specification. Initialize to 0. Once initialized, do not write to this word.
R_OVERRUNS Word Format This word is read-only and is maintained by the RALP Field (Bits) R_OVERRUNS (15:0) Description 16-bit rollover count of the occurrences of an overrun on this queue. This is the atmfCESBufOverflows counter in the CES specification. Initialize to 0. Once initialized, do not write to this word.
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R_POINTER_REFRAMES Word Format This word is read-only and is maintained by the RALP Field (Bits) R_POINTER_REFRAME (15:0) Description 16-bit rollover count of the occurrences of pointer reframes on this queue. This is the atmfCESPointerReframes counter in the CES specification. Initialize to 0. Once initialized, do not write to this word.
R_PTR_PAR_ERR Word Format This word is read-only and is maintained by the RALP Field (Bits) R_PTR_PAR_ERR (15:0) Description 16-bit rollover count of the occurrences of pointer parity errors on this queue. This is the atmfCESPointerParityErrors counter in the CES specification. Initialize to 0. Once initialized, do not write to this word.
R_MISINSERTED Word Format This word is read-only and is maintained by the RALP Field (Bits) R_MISINSERTED (15:0) Description 16-bit rollover count of the occurrences of misinserted cells on this queue. This is the atmfCESMisinsertedCells counter in the CES specification. Initialize to 0. Once initialized, do not write to this word.
R_ROBUST_SN Word Format This word is read-only and is maintained by the RALP Field (Bits) Reserved (15) Description Used to indicate when the first cell is received on a RSN connection.
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Field (Bits) R_RSN_RESUME (14) R_RSN_CHAN_PTR (13:9) R_RSN_WRT_PTR (8:0)
Description Indication that the stored cell is the first cell after an underrun. Pointer to the channel number in which to start if dropping a previously stored cell. Pointer to the frame to which the cell receiver is writing for Robust SN processing.
R_RD_PTR_LAST Word Format This word is read-only and is maintained by the RALP Field (Bits) Not used (15:9) R_RD_PTR_LAST (8:0) Description Driven with a 0. Mask on reads to maintain future software compatibility. Pointer to the frame that was last read when the last cell was received. This is used to determine whether more than 6 cells have been lost when a SN error occurs to help maintain bit integrity through underrun.
7.2.12 R_OAM_QUEUE Organization: 256 cells x 64 bytes Base address within A1SP: E000H Index: 20H Type: Read/Write Function: The receive signaling queue stores the signaling received from the UTOPIA interface. Initialization: It is not necessary to initialize this structure. Format: Two data bytes per word
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R_OAM_QUEUE Format Offset 00000H 00010H . . . 01FFFH Name R_OAM_CELL_0 R_OAM_CELL_1 . . . R_OAM_CELL_255 Description Receive OAM cell 0 Receive OAM cell 1 . . . Receive OAM cell 255
R_OAM_CELL_n Format Offset Word 0 Word 1 Word 2 Word 3 . . . Word 26 Word 27 CRC_10_PASS Word Format Field (Bits) CRC_10_PASS (15) Not used (14:0) Description The CRC_10_PASS bit is set if the cell passes the CRC-10 check. Write with a 0 to maintain future software compatibility. Bits (15:8) Header 1 Header 3 Header 4 (HEC) Payload 1 . . . Payload 47 CRC_10_PASS Bits (7:0) Header 2 Header 4 Blank Payload 2 . . . Payload 48
7.2.13 RESERVED (Receive Data Buffer) This structure is reserved and must be initialized to 0 at initial setup. If RX_COND for some channels is set to "11" (insert old data during underrun),
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then those channels may need to be initialized to some other value if "0" data is unacceptable, since all the queues will reset to the underrun state. Software modifications to this location after setup will cause incorrect operation. Organization:Each line has a separate receive data buffer consisting of 512 frame buffers. Each frame buffer can store 32 bytes. For E1 structured data applications, this allows storage of 512frames or 32 multiframes of data. Structured T1 applications use only the first 24 bytes of each frame buffer for data storage. Also, only the first 24 frame buffers of every 32 are used to store T1 structured data frames. This provides 384 frames of storage, or 16 multiframes. Unstructured applications store 256 bits of data in every frame buffer. For E1 with T1 signaling, use T1 structure but with 32 channels. Base address within A1SP: 10000H Index (line): 2000H Type: Read/Write Function: The data buffers store receive data information. The data is stored in the buffers in the order that they will be played out to the lines. Initialization: Initial to 0 at startup. If RX_COND for some channels is set to "11" (insert old data during underrun), then those channels may need to be initialized to some other value if "0" data is unacceptable. Format: Two data bytes per word.
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R_DATA_BUFFER_n Word Format Field (Bits) R_DATA_H (15:8) Receive data for: Channel = (offset mod 16) x 2 + 1. E1 frame = (offset mod 256) / 16. T1 frame = (offset mod 512) / 16. E1 multiframe = (offset mod 8192) / 256. T1 multiframe = (offset mod 8192) / 512. Line = offset / 8192. E1 offset = line x 8192 + multiframe(E1) x 256 + frame(E1) x 16 + (chan-1) / 2. T1 offset = line x 8192 + multiframe(T1) x 512 + frame(T1) x 16 + (chan-1) / 2. R_DATA_L (7:0) Receive data for: Channel = (offset mod 16) x 2. E1 frame = (offset mod 256) / 16. T1 frame = (offset mod 512) / 16. E1 multiframe = (offset mod 8192) / 256. T1 multiframe = (offset mod 8192) / 512. Line = offset / 8192. E1 offset = line x 8192 + multiframe(E1) x 256 + frame(E1) x 16 + channel / 2. T1 offset = line x 8192 + multiframe(T1) x 512 + frame(T1) x 16 + channel / 2. Description
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8
CONFIGURING THE LINE INTERFACE The line interface block is responsible for passing the TDM data between the A1SP blocks and converting it to the appropriate protocol used on the external lines. The mode of the module is determined by the value of the LINE_MODE pins during hardware reset. This mode can be read by software in the LINE_MODE bits of the LINE_MODE_REG (0x80210). The following encoding is used: LINE_MODE [1:0] "00" "01" Line Interface Mode Direct Low Speed SBI AAL1gator-32 Supports 16 T1/E1 links. Supports 32 T1/E1 links or 2 T3 links. Supports 32 T1/E1 links. Supports 2 T3/E3/STS1/STM-0 links. AAL1gator-8 Supports 8 T1/E1 links. Not Supported Supports 8 T1/E1 links. Supports 1 T3/E3/STS1/STM-0 link. AAL1gator-4 Supports 4 T1/E1 links. Not Supported Supports 4 T1/E1 links. Supports 1 T3/E3/STS1/STM-0 link.
"10" "11"
H-MVIP High Speed
Note: SBI mode is not supported in the AAL1gator-8 and the AAL1gator-4. Figure 14 shows the block diagram for the Line Interface Block of the AAL1gator-32. The block consists of the SBI Block, an H-MVIP Block and mux/demux logic.
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Figure 14 - Line Interface Block Architecture
8
A1SP 3
8
A3 A2
8
SBI DROP BUS
8
A1SP 2
8
32 8
SBI BLOCK
SBI ADD BUS
8
A1SP 1
8
A1
8 16 16 8 8 8 16
MVIP
Lines(0:7) Lines(8:15)
A1SP 0
8
16
8
B0
The A0 to A3 mux/demux logic selects between SBI links and non-SBI links. The B0 mux/demux logic selects between the H-MVIP data or external direct links. The upper 16 lines can only be used in H-MVIP, or SBI mode. In high speed mode, external lines 0, and 2 are used, but they are mapped to internal links 0 and 16. 8.1 Conventions The following conventions are used in this section: The 32/8/4 lines, which connect the AAL1_LI to the A1SP blocks, are called local links. The lines on the external interface are called external lines. The direction from the local links to the external line interface is call the transmit direction. The direction from the external line interface to the local links is called the receive direction. The individual data streams within the SBI interface are known as tributaries. Once inside the AAL1_LI, these data streams are known as links. In SBI mode links and tributary numbering starts at `1'.
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A0
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With respect to the SBI interface the Add direction is the one where data is placed onto the SBI, the Drop direction is the one where data is extracted from the SBI. This block is intended to be used as a Link Layer Device on the SBI. With respect to the internal links, the lower group refers to links 0 through 15 and the upper group refers to links 16 through 31. Note that when using the SBI bus the link numbering starts at `1'. Therefore when using SBI the lower group refers to links 1 through 16 and the upper group refers to links 17 through 32. 8.2 Register Summary Table 6 is a summary of the normal mode registers that configure the AAL1gator Line Interface. Table 7 summarizes the bit fields within these registers. Note that there is an LS_Ln_CFG_REG for each of the 16/8/4 low speed lines. Table 6 - Internal Line Configuration Registers Address 0x80200 - 0x8020F 0x80210 Register Description Low Speed Line n Configuration Registers Line Mode Register Register Mnemonic LS_Ln_CFG_REG LINE_MODE_REG
Table 7 - Internal Line Configuration Register Bits Register Mnemonic LS_Ln_CFG_REG LINE_MODE_REG Bit Bit 1 Bit 0 Bit 1:0 Type R/W R/W RO Function MVIP_EN MF_SYNC_MODE LINE_MODE Default 0 0 00
Table 8 is a summary of the memory mapped configuration structures that configure the AAL1gator Line Interface. There is a LIN_STR_MODE register for each of the (up to) eight lines (n = 0, ..., 7) within each A1SP. Writes to these registers will not take effect until the An_CMDREG_ATTN bit is set in the An_CMD_REG for that A1SP. Note that the addresses listed below are the offsets within each A1SP address space.
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Table 8 - A1SP and Line Configuration Structures Summary Address 0001h Name HS_LIN_REG Org 1 word Size Description
2 bytes The High Speed Line Register provides overall mode information. 2 bytes The Line Structure Mode register identifies which data structure type will be supported for each line. This is selectable on a line basis.
0010h 0017h
LIN_STR_MODE_n
1 word
The bit fields of the LS_Ln_CFG_REG and LIN_STR_MODE registers and the modes in which these bits are applicable are shown in Table 9. A "" denotes that the field is selectable for that mode. An "n/a" denotes that the field is ignored for that mode. External memory should be cleared to all zeros at initialization. Please see each mode's section for a description of the bit fields applicable to that mode. Table 9 - Applicability of Line Configuration Bits Bit Field Direct Low Speed SDF LS_Ln_CFG_REG: 1 0 15 14 13 12 11 10 9 8 MVIP_EN MF_SYNC_MODE LOW_CDV REF_VAL_ENABLE T1_MODE E1_WITH_T1_SIG HI_RES_SYNTH Reserved MF_ALIGN_EN Not Used n/a 0 0 0 n/a n/a n/a n/a 0 n/a 0 0 n/a n/a 0 0 0 0 n/a 0 n/a 0 0 0 n/a n/a n/a n/a n/a 0 n/a 0 UDF SBI H-MVIP High Speed
LIN_STR_MODE:
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Bit
Field
Direct Low Speed SDF UDF n/a 10
SBI
H-MVIP
High Speed n/a n/a
7 6:4 3 2 1:0 8.3
GEN_SYNC CLK_SOURCE_TX CLK_SOURCE_RX SRTS_EN FR_STRUCT
0
0
0 n/a n/a 0
Direct Low Speed Mode Direct Low Speed mode is used for interconnecting to standard T1 or E1 framers and to devices which support the MVIP-90 protocol. For the AAL1gator, this mode is mainly a pass through mode between the external 16/8/4 lines and the lower 16/8/4 local links. In the AAL1gator-32, the lower 16 local links connect to A1SP 0 and A1SP 1. The second RAM interface of the AAL1gator-32 cannot be used and is not needed when using Direct Low Speed Mode. DS1 / E1 Links When configured in Direct Low Speed Mode, the AAL1gator-32, AAL1gator-8 and AAL1gator-4 support sixteen, eight and four DS1/E1 links respectively where each link comprises a clock, data, frame pulse, and signaling pin for each direction. In addition, low speed clear channel data streams can be passed in this mode. A common clock pin is also available, which can be shared across all receive lines or all transmit lines and is selectable on a per line basis Some framers also share a clock and signaling pin, where the clock pin becomes a signaling pin when signaling is required or remains as a clock pin when individual clocks per line are required. When this pin carries signaling information a common clock is used, which is shared across all lines. This option can be configured on a per line basis. MVIP-90 2 Mbps MVIP mode is also supported where the line is handled in accordance with the MVIP-90 specification. MVIP mode can be individually selected per line for all lines. Tri-stating of individual time slots is not supported. There is a common 4 MHz clock and a common framing reference signal.
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Unstructured J2 Using the clock and data pins in Direct Low Speed Mode, the AAL1gator devices support unstructured J2 transport over ATM. The AAL1gator-32 supports up to six unstructured J2 lines while the AAL1gator-8 and AAL1gator-4 support three unstructured J2 lines. 8.3.1 Line Format and Frame Structure Selection between T1 or E1 clock/data lines is based on the value of T1_MODE in the LIN_STR_MODE memory register for each line. Selection between standard clock/data or MVIP-90 line format is based on the value of MVIP_EN in the LS_Ln_CFG_REG register for each line. The frame structure in Direct Low Speed Mode can be Structured Data Format - Frame (SDF-FR), Structured Data Format - Multiframe (SDF-MF) or Unstructured Data Format - Multi-Line (UDF-ML) and is determined by the value of FR_STRUCT[1:0] in the LIN_STR_MODE memory register for each line as follows: FR_STRUCT[1:0] 00 01 SDF-FR Frame Structure Not Used. A structured connection where CAS signaling is not being transported (basic service). An unstructured clear channel bit stream for line speeds < 15 Mbps (supports 8 lines per A1SP if all are under 2.5 Mbps). A structured connection where CAS signaling is being transported. Description
10
UDF-ML
11 Notes: * *
SDF-MF
MVIP-90 lines can not be configured for UDF-ML. If a mixture of CAS and non-CAS connections are being made on the same line, then put the line in SDF-MF mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for the connections not carrying CAS.
Table 10 summarizes configuration of line format and frame structure.
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Table 10 - Configuration of Line Format and Frame Structure Mode T1 SDF-FR SDF-MF UDF-ML E1 SDF-FR SDF-MF UDF-ML J2 MVIP90 UDF-ML SDF-FR SDF-MF T1_MODE 1 1 n/a 0 0 n/a n/a 0 0 MVIP_EN 0 0 0 0 0 0 0 1 1 FR_STRUCT[1:0] 01 11 10 01 11 10 10 01 11
8.3.2 Line Clock Source Several clocking options exist in this mode and are controlled by the value of the CLK_SOURCE bits in the LIN_STR_MODE register for each line. 8.3.2.1 Receive Line Clock Source In the receive direction, the line clock source has two options based on the value of the CLK_SOURCE_RX bit in LIN_STR_MODE: CLK_SOURCE_RX 0 1 Function The line receives its clock from the external clock (RL_CLK[n] pin) associated with that line. The line receives its clock from the common external clock (CRL_CLK pin).
8.3.2.2 Transmit Line Clock Source In the transmit direction, eight possible options exist and are controlled by the value of the CLK_SOURCE_TX bits in the LIN_STR_MODE memory register for each line. When read by the A1SP, this value will override the setting defined by the TLCLK_OE input pin. If switching from an external to an internal clock or visa versa, make sure there are not two clocks driving simultaneously. The options are listed below:
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CLK_SOURCE_TX[2:0 ] 000 001 010
Function Clock is an input on pin TL_CLK[n]. Clock is an input on pin RL_CLK[n] (loop timing mode). Clock is internally synthesized as a nominal T1 or E1 clock based on SYS_CLK and the value of T1_MODE. The clock is output on the TL_CLK[n] pin. Clock is internally synthesized based on the received SRTS values. The clock is output on TL_CLK[n] pin. Clock is internally synthesized using the adaptive algorithm which uses receive buffer depth to control TL_CLK[n]. The clock is output on TL_CLK[n] pin. Clock is internally synthesized based on values received on the external clock control interface. This mode is used for external implementations of SRTS or Adaptive clocking. The clock is output on TL_CLK[n] pin. The line uses the common external clock (CTL_CLK pin). The line uses the common external clock (CTL_CLK pin) and signaling data (TL_SIG[n]) is driven onto the TL_CLK[n] pin.
011 100
101
110 111
8.3.2.2.1 AAL1 Clock Generation Control The Clock Generation Control (CGC) block is responsible for generating the synthesized transmit line clocks. Options "010" through "101" for CLK_SOURCE_TX involve the CCG block. A given line clock is synthesized internally using a 38.88 MHz system clock (SYS_CLK). Only T1 or E1 clocks can be generated internally. Any other frequency clock must be generated externally and passed into the AAL1gator as an input. The frequency of the synthesized clock can be controlled via an external input, the internal SRTS algorithm, or the internal adaptive algorithm. Each line clock can be controlled independently. To assist an external source in determining what frequency to use, SRTS and adaptive information is output using the external interface.
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8.3.2.2.1.1 Synchronous Residual Time Stamp The SRTS block within the CGC block receives SRTS values and uses the values to determine the frequency to be synthesized. When enabled, the local SRTS values, which are calculated within this SRTS block, are subtracted from the SRTS values received in the cells received by RALP, which represent the remote SRTS values. This SRTS difference is sent by the SRTS block to the Frequency Synthesizer to indicate what frequencies should be synthesized for each line. The SRTS difference is also played out externally. SRTS functionality is enabled by setting the SRTS_EN bit in the LIN_STR_MODE memory register. SRTS is supported for unstructured data formats on a per-line basis. Leave this bit clear for structured data formats. SRTS_EN 0 1 Function SRTS disabled. The CSI bits of the odd transmit AAL1 cells are set to 0 and the received SRTS bits are ignored. SRTS enabled. The insertion of the transmit SRTS bits is enabled for this line and the received SRTS bits are accumulated.
8.3.2.2.1.2 Adaptive Clocking Algorithm The Adaptive block determines the appropriate line clock frequencies based on the buffer depth received from the A1SP. Every time a cell is received on a particular line, the Adaptive block is given the current depth of the receive buffer. If the buffer depth is increasing, then the local line clock is running slower than the remote line clock. If the buffer depth is decreasing, then the local line clock is running faster than the remote line clock. Therefore, the Adaptive block will adjust the local line clock according to the buffer depth by passing the appropriate value to the Frequency Synthesizer. Adaptive clocking is only supported for unstructured connections inside the AAL1gator. If adaptive clocking is desired for structured connections, it will need to be processed externally. 8.3.2.2.1.3 Frequency Synthesizer The Frequency Synthesizer block synthesizes any one of 256 possible frequencies centered around either the T1 or E1 nominal frequency based upon an 8-bit select value. The synthesized frequency is derived from the 38.88 MHz system clock.
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The Frequency Synthesizer block receives an 8-bit two's complement number to select a frequency setting. Although possible (with 8 bits) to input a value of -128 to 127 this input is limited internally to -83 to 88 for T1 and -128 to 111 for E1. This is done in order to not exceed the frequency range specification of +/200ppm for T1 and +/- 100ppm for E1. Based on this value, the Frequency Synthesizer synthesizes a clock for each line. The line frequency is synthesized by dividing down the 38.88 MHz system clock. The method for dividing down the system clock is dependent on whether the line is in T1 or E1 mode. The synthesizers can be set to operate in normal or high resolution mode based on the value of HI_RES_SYNTH in the LIN_STR_MODE memory register. HI_RES_SYNTH 0 Function Normal mode: only the 4 high order bits of the frequency setting value are monitored to generate 1 of 16 frequencies. SRTS requires normal mode. High resolution mode: all 8 bits are monitored to generate 1 of 256 frequencies. Adaptive clocking requires high resolution mode.
1
Table 11 indicates the resolution modes that must be used in the four CLK_SOURCE_TX options that use the CGC block. A "" indicates that either normal or high resolution mode can be selected for that clock source option. Table 11 - Frequency Synthesis Resolution Modes CLK_SOURCE_TX[2:0] 010 011 100 101 8.3.3 Synchronization 8.3.3.1 Receive Direction The Line Interface Block accepts deframed data from the external lines. The data, signaling and synchronization signals are received from the external interface. The external lines can support data rates up to 15 Mbps per line. The falling edge of RL_CLK[n] is used to clock in the data and is used as the active Synthesized Clock Type Nominal T1 or E1 SRTS Adaptive Externally controlled HI_RES_SYNTH 0 1
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edge for all receive logic in this mode. For structured data, the Line Interface Block uses the external synchronization input signals (RL_SYNC[n]) as either frame pulses or multi-frame pulses. Whether the Line Interface Block interprets RL_SYNC[n] as a frame pulse or a multi-frame pulse is determined by the value of MF_SYNC_MODE in the LS_Ln_CFG_REG register for that line. MF_SYNC_MODE 0 1 Notes: * If the line is configured for UDF-ML mode (unstructured), the data will be passed as a clear channel bit stream and RL_SYNC[n] will be ignored. In this case, leave MF_SYNC_MODE clear as default. In the receive direction, synchronization is always controlled by the external line interface. Function Sync signals are frame sync signals. Sync signals are multi-frame sync signals.
*
In T1/E1 mode, the first time RL_SYNC[n] is sampled high after being low indicates the first bit of a frame or multi-frame. In MVIP-90 mode, the first time RL_SYNC[n] is sampled low after being high indicates the first bit of a frame. For T1 structured data, a frame is completed every 193 bits. For E1 or MVIP-90 structured data, a frame is completed every 32 bytes. 8.3.3.2 Transmit Direction In the line transmit direction, for structured data, the Line Interface Block takes the TL_SYNC[n] signal and depending on the value of MF_SYNC_MODE, interprets the signal as either a frame pulse or multi-frame pulse. The MF_SYNC_MODE bit from section 8.3.3.1 configures both the receive and transmit directions and its encoding is repeated below: MF_SYNC_MODE 0 1 Function Sync signals are frame sync signals. Sync signals are multi-frame sync signals.
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Note: If the line is configured for UDF-ML mode (unstructured), the data will be played out as a clear channel bit stream and TL_SYNC[n] will be ignored. In this case, leave MF_SYNC_MODE clear as default. In the transmit direction, synchronization can be controlled from either the local link side or the external line side based on the value of GEN_SYNC in the LIN_STR_MODE memory register. GEN_SYNC 0 1 Function TL_SYNC[n] is received from the corresponding external framing device and is an input for this line. TL_SYNC[n] is generated internally by the AAL1gator and is an output for this line.
Note: If no synchronization is required, then leave GEN_SYNC clear as default. In T1/E1 mode, the first time TL_SYNC[n] is sampled high after being low indicates the first bit of a frame or multi-frame. In MVIP-90 mode, the first time TL_SYNC[n] is sampled low after being high indicates the first bit of a frame. For T1 structured data, a frame is completed every 193 bits. For E1 or MVIP-90 structured data, a frame is completed every 32 bytes. 8.3.4 CAS Signaling This section is applicable to structured data only. Unstructured data is sent and received without regard to the byte alignment of data within a frame and is placed in the frame buffer in the order in which it arrives. In the receive direction, signaling is accumulated on RL_SIG[n] from the framer over an entire multi-frame, so signaling only has to be sampled once per multiframe. The AAL1gator reads signaling during the last frame of every multi-frame. The AAL1gator reads the signaling nibble for each channel when it reads the last nibble of each channel's data. In the transmit direction, signaling data is driven on TL_SIG[n] for all frames of any multi-frame and will change only on multi-frame boundaries. The signaling nibble is valid for each channel when the last nibble of each channel's data is being driven. In T1 mode, a multi-frame can either be 12 or 24 frames of 24 timeslots depending on if the line is in Super Frame (SF) or Extended Super Frame (ESF) mode. The AAL1gator accommodates the T1 Super Frame (SF) mode by treating it like the Extended Super Frame (ESF) format and updating signaling
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data only on the last frame of odd SF multiframes. Figure 15 shows an example of a T1 frame in the receive direction. Figure 15 - Capture of T1 Signaling Bits
Line Signals During the Last Frame of a Multiframe
RL_SER (timeslots)
0
1
2
... ... ...
21
22
23
ABCD RL_SIG XXXX ABCD XXXX Channel 1 XXXX ABCD Channel 2
Channel 0
ABCD ABCD ABCD XXXX Channel 21 XXXX Channel 22 XXXX Channel 23
XXXX - indicates signaling is ignored
Figure 16 shows an example of a T1 frame in the transmit direction. Figure 16 - Output of T1 Signaling Bits
Line Output Signals During Every Frame (timeslots)
TL_SER
0
1
2
... ... ...
21
22
23
ABCD TL_SIG XXXX ABCD XXXX Channel 1 XXXX ABCD Channel 2
Channel 0
ABCD ABCD ABCD XXXX Channel 21 XXXX Channel 22 XXXX Channel 23
XXXX - indicates signaling is invalid
Normally an E1 multiframe consists of 16 frames of 32 timeslots, where signaling changes on multiframe boundaries. A special case of E1 mode exists that permits the use of T1 signaling with E1 framing based on the value of E1_WITH_T1_SIG in the LIN_STR_MODE memory register. When E1_WITH_T1_SIG is set and the line is in E1 SDF-MF mode, the AAL1gator will use a multiframe consisting of 24 frames of 32 timeslots. E1_WITH_T1_SIG 0 1 Function Use E1 signaling. Signaling is updated every 16 frames. Use T1 signaling. Signaling is updated every 24 frames instead of every 16 frames.
Figure 17 shows an example of an E1 frame in the receive direction.
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Figure 17 - Capture of E1 Signaling Bits
Line Signals During the Last Frame of a Mult iframe (timeslots)
RL_SER
0
1
2
... ... ...
29
30
31
ABCD RL_SIG XXXX ABCD XXXX Channel 1 XXXX ABCD Channel 2
Channel 0
ABCD ABCD ABCD XXXX Channel 29 XXXX Channel 30 XXXX Channel 31
XXXX - indicates signaling is ignored
Figure 18 shows an example of an E1 frame in the transmit direction. Figure 18 - Output of E1 Signaling Bits
Line Output Signals During Every Frame (timeslots)
TL_SER
0
1
2
... ... ...
29
30
31
ABCD TL_SIG XXXX ABCD XXXX Channel 1 XXXX ABCD Channel 2
Channel 0
ABCD ABCD ABCD XXXX Channel 29 XXXX Channel 30 XXXX Channel 31
XXXX - indicates signaling is invalid
Note: The AAL1gator treats all 32 timeslots identically. Although E1 data streams contain 30 timeslots of channel data, 1 timeslot of framing (timeslot 0) and one time slot that can either be signaling or data (time slot 16), data and signaling for all 32 timeslots are stored in memory and can be sent and received in cells. 8.3.5 Other Per-Line Options Multiframe Alignment By default, in SDF-MF mode, only the CDVT value is taken into account when determining when to play out data. This provides predictable delay but causes a difference in MF alignment on both sides of the ATM network. To align the MF structure in the cell with the external MF pulse, MF_ALIGN_EN should be set. If MF_ALIGN_EN is set, then RALP will not only queue up one CDVT worth of time of data but will also delay the write pointer to the next MF boundary. This method will ensure MF alignment across the ATM network but will add variable delay that could be between 0 and 3 ms. Usually, MF_ALIGN_EN is not set because predictable delay is more important than MF alignment and a variable delay is undesirable. Note that
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MF_ALIGN_EN is only used for lines in SDF-MF mode. MF_ALIGN_EN is encoded as follows: MF_ALIGN_EN 0 1 Function Only the CDVT value is taken into account when determining when to play out data. The CDVT and the multiframe boundaries are taken into account; the data is aligned with the next MF boundary after CDVT.
Reference Value Generation This bit enables the generation of the reference value for this line used when adding queues. This bit is used for structured modes only. REF_VAL_ENABLE 0 1 Function Reference value generation is disabled. The first cell of a queue is scheduled relative to frame 0. Reference value generation is enabled. The reference value increments to emulate a single DS0 queue every time the current frame value is equal to the current reference value.
Low CDV for Unstructured Mode For UDF-ML lines, the LOW_CDV bit of the LIN_STR_MODE memory register can be set to cause cells to be scheduled every 47 bytes instead of using frame based scheduling. This eliminates the CDV caused by the scheduler. This mode can only be used in UDF-ML mode when BYTES_PER_CELL is 47. This mode cannot be used when the queue is configured for partial cells or for AAL0 mode. LOW_CDV 0 1 Function Unstructured line is not in low CDV mode. AAL1gator uses frame based scheduling. Unstructured line is in low CDV mode. AAL1gator uses byte based scheduling where cells are scheduled every 47 bytes.
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8.4
SBI Mode The Scaleable Bandwidth Interconnect (SBI) is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH virtual tributary structure is used to carry T1 and E1 links. Unchannelised DS3 payloads follow a byte synchronous structure modeled on the SONET/SDH format. The multiplexed links are separated into three Synchronous Payload Envelopes (SPEs). Each envelope may be configured independently to carry up to 28 T1s, 21 E1s or a DS3. Full details of the operation of the SBI interface are provided in the SBI Compatibility Specification [6]. The Scaleable Bandwidth Interconnect (SBI) Line Interface mode is used in the AAL1gator-32 to interface to the PM8315 TEMUX chip or any other PHY layer chip that has an SBI Interface on it. The SBI Block within the Line Interface Block interfaces to the SBI bus on one side and inputs/outputs up to 32 T1 links, 32 E1 links or two DS3 links to the A1SP blocks. It can also support a mix of links made up of a combination of 16 T1 or E1 links or 1 DS3 link. In SBI mode the upper 16 links make up one configurable unit and the lower 16 links make up another unit. The SBI interface block is made up of 4 main components: Extract SBI Block (EXSBI), Insert SBI BLOCK (INSBI), Parallel In to Serial Out Converter (PISO), and Serial In to Parallel Out Converter (SIPO). There are two PISO and SIPO blocks, each of which processes 16 links. See Figure 19 for the SBI Block architecture.
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Figure 19 - SBI Block Architecture
Link Type To A1SP #3 and #2
16
To A1SP #1 and #0
PISO (16 lines)
EXSBI
16
PISO (16 lines)
Link Type Link Type
SBI Drop Bus
3 SPEs
2 SPEs
From A1SP #3 and #2
INSBI
16
SIPO (16 lines) SIPO (16 lines)
Link Type
SBI Add Bus
3 SPEs
2 SPEs
From A1SP #1 and #0
16
The EXSBI is responsible for extracting links from the SBI Drop bus and switching them to either SPE#1 which is mapped to the lower 16 links or SPE#2 which is mapped to the upper 16 links. The links are output to an internal parallel bus. The INSBI is responsible for taking links from the internal parallel bus and inserting the remapped links to the SBI Add bus. The PISO block is responsible for taking the internal parallel bus from EXSBI and serializing the links for the local link interface. It is also responsible for generating the receive serial clocks for the local links going to each A1SP block. There is one PISO block for each group of 16 links. The SIPO block is responsible for taking the serial links from the local link interface and putting them onto the internal parallel bus to INSBI. It is also responsible for handling the generation of the transmit serial clock for the local links coming from the A1SP blocks, if the local link is receiving its transmit timing from the SBI. There is one SIPO block for each group of 16 links.
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8.4.1 Programming the SBI Interface To have a clean start up, the following programming sequences are recommended when setting up the SBI interface: General Rules * After clearing Chip Software Reset, the internal rams go through an internal initialization process that takes at least 500 s. The BUSY bit in the Extract/Insert Tributary RAM Indirect Access Control Registers (0x80404/0x80504) should be polled until low before attempting any INSBI/EXSBI read and write accesses. General SBI control registers outside of EXSBI/INSBI can be configured at any time. At initialization, the SBI tributary receiver should be enabled before the corresponding SBI tributary transmitter (i.e. - configure the EXSBI before configuring the INSBI) If DC_EN in the Extract/Insert Control Register (0x80400/0x80500) is disabled and an overrun/underrun condition is reported for a link, the link should be reset by writing to the tributary control register for the tributary corresponding to that link. If DC_EN is set, then the tributary will automatically be reset. To configure individual link to be in synchronous mode, the SPEn_SYNCH bit in the SBI_BUS_CFG_REG (0x80300) must be clear and the corresponding SYNC_LINK[n] bit in SBI_SYNC_LINK_REGL/H (0x80304/0x80305) must be set. Furthermore, the SYNCH_TRIB bit in the Insert Tributary Control Indirect Access Data Register (0x80506) must also be set. It is important to note that in synchronous mode, a tributary must derive its clocking from the SBI bus. In other words, that tributary must be configured to be clock slave to the SBI bus by clearing the CLK_MSTR bit in both Extract and Insert Control RAM Indirect Access Data (0x80406/0x80506) registers The TS_EN bit in SBI Bus Configuration Register (0x80300) must be set to globally enable tributary to link mapping. If this bit is set then mapping may occur on a tributary by tributary basis. If this bit is a zero, which is the default value, then the first 16 links are mapped to the first 16 links of SPE1 and the upper 16 links are mapped to the first 16 links of SPE2.
* *
*
*
*
*
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*
There is also a TS_EN bit in the Extract/Insert Control Register (0x80400/0x80500), which operates in a similar fashion. To map an individual tributary to a link, both TS_EN bit on the Extract and on the Insert side must be set in addition to the global TS_EN bit in the SBI Bus Configuration Register.
Tributary Mapping Sequence 1. Configure all tributaries in the SBI Extract Tributary Mapping RAM by following the steps described in section 8.4.3.2.1. Configure all tributaries in the SBI Insert Tributary Mapping RAM by following the steps described in section 8.4.4.2.1. 2. Set the global TS_EN bit in the SBI Bus Configuration Register (0x83000). 3. Set the global TS_EN bit in the EXSBI/INSBI Control Registers (0x84000/0x85000). 4. Configure all of the SBI Extract Tributary Control RAM by following the steps described in section 8.4.3.2.2. Configure all of the SBI Insert Tributary Control RAM by following the steps described in section 8.4.4.2.2. 5. Enable the SPEs last by setting the SPEn_ENBL bits in the SBI Bus Configuration Register (0x83000). Note: It is important to note that if tributary mapping needs to be done on any tributary, then all tributary mapping must be done to all tributaries in the SBI (i.e., 84 tributaries if all 3 SPEs are T1). Synchronous Configuration Even though there is no strict sequence to be followed when configuring a link to be synchronous or asynchronous mode, there are a few important notes to be aware of: * If any of the 32 links is configured for synchronous mode, then the DC_EN and DC_INT_EN bits in the Extract/Insert Control Registers (0x84000/0x85000) must be disabled by clearing the bits. This must be done because Depth Check logic does not support synchronous mode. If any link/tributary within an E1 SPE is in synchronous mode, the C1FP pulses must not be 500 s apart (2Khz rate) but 6 ms instead, which is once every 48 SBI frames.
*
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8.4.2 General SBI Configuration General SBI configuration is performed by programming bits within the following internal registers: Table 12 - General SBI Register Memory Map Offset Register Description Register Mnemonic
These registers are selected when the address = 0x803XX. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D SBI Bus Configuration Register SBI Link Configuration Register SBI Link Disable Low SBI Link Disable High SBI Sync Link Low SBI Sync Link High Reserved Reserved SBI Extract Bus Alarm Interrupt Register Low SBI Extract Bus Alarm Interrupt Register High SBI Extract Bus Alarm Status Register Low SBI Extract Bus Alarm Status Register High SBI Insert Bus Alarm Insert Register Low SBI Insert Bus Alarm Insert Register High The default configuration is as follows: Bit SPE1_TYP[1:0] SPE2_TYP[1:0] SPE3_TYP[1:0] SPE1_ENBL SPE2_ENBL SPE3_ENBL Register SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) Value 00 00 00 0 0 0 EXT_ALRM_INTL EXT_ALRM_INTH EXT_ALRM_STATL EXT_ALRM_STATH INS_ALRM_REGL INS_ALRM_REGH SBI_BUS_CFG_REG SBI_LNK_CFG_REG SBI_LINKL_DISABLE SBI_LINKH_DISABLE SBI_SYNC_LINKL SBI_SYNC_LINKH
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Bit SPE1_SYNCH SPE2_SYNCH SPE3_SYNCH CLK_MSTR TS_EN FST_CK_FRQL [1:0] CKOUT_KILLL
Register SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_BUS_CFG_REG (0x80300) SBI_LNK_CFG_REG (0x80301) SBI_LNK_CFG_REG (0x80301)
Value 0 0 0 0 0 00 00 0 00 00 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
LINK_TYPL[1:0] SBI_LNK_CFG_REG (0x80301)
LINK_TYPH[1:0] SBI_LNK_CFG_REG (0x80301) FST_CK_FRQH SBI_LNK_CFG_REG (0x80301) [1:0] CKOUT_KILLH LINK_DIS[15:0] SBI_LNK_CFG_REG (0x80301) SBI_LINK_DIS_REGL (0x80302)
LINK_DIS[31:16] SBI_LINK_DIS_REGH (0x80303) SYNC_LINK[15:0] SBI_SYNC_LINK_REGL (0x80304) SYNC_LINK [31:16] SBI_SYNC_LINK_REGH (0x80305)
SBI_ALARM_INT EXT_ALRM_INT_REGL (0x80308) [15:0] SBI_ALARM_INT EXT_ALRM_INT_REGH (0x80309) [31:16] SBI_ALRM_STAT EXT_ALRM_STAT_REGL (0x8030A) [15:0] SBI_ALRM_STAT EXT_ALRM_STAT_REGH (0x8030B) [31:16] SBI_ALRM_INS INS_ALRM_REGL (0x8030C) [15:0] SBI_ALRM_INS INS_ALRM_REGH (0x8030D) [31:16]
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The default indicates that all three Synchronous Payload Envelopes are configured for T1 links and the FASTCLK input operates at a frequency of 51.84 MHz. The three SPEs are disabled in the default state. 8.4.2.1 SBI Bus Configuration and Tributary Override Control The SBI bus contains 3 Synchronous Payload Envelopes (SPE) which can be configured to be E1, T1, or DS3. SBI_BUS_CFG_REG (0x80300) defines the payload type for each SPE, enables each SPE and provides some override control for the individual tributaries. SPEn Payload Type The SBI bus contains 3 Synchronous Payload Envelopes (SPE) which can be configured to be E1, T1, or DS3. The SPEn_TYP fields identify the payload type of each SPE. The encoding for SPEn_TYPE is: Payload Type T1 E1 DS3 Reserved SPEn Enable The SPEn_ENBL field is used to enable or disable an entire SPE on the SBI. All SPEs default to being disabled. SPEn_ENBL 0 1 SPEn is disabled. SPEn is enabled. Function SPEn_TYP Value b"00" b"01" b"10" b"11"
Synchronous Mode for All Tributaries within SPEn The SPEn_SYNCH field is used to specify that all tributaries within the SPE should operate in synchronous mode. This can be used as an override mechanism for configuring all tributaries within the particular SPE to be in synchronous mode irrespective of the TRIB_CTL settings.
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SPEn_ENBL 0
Function The value of the TRIB_CTL settings will be used when determining if an individual tributary within SPEn is in synchronous mode. All tributaries within SPEn will be forced to be in synchronous mode.
1
Clock Master Mode for All Tributaries within SPEn The CLK_MSTR field is used as an override mechanism for configuring all tributaries to be clock masters irrespective of the TRIB_CTL settings. This TRIB_CTL settings default so that all tributaries are clock slaves. CLK_MSTR 0 Function The value of the TRIB_CTL settings will be used when determining if an individual tributary within SPEn is a clock master. All tributaries within SPEn will be forced to be clock masters.
1
One to One Tributary to Link Mapping The TimeSwitch Enable (TS_EN) field is used as an override mechanism for configuring Tributary to Link mapping to be one to one irrespective of the TRIB_MAP settings. TS_EN 0 Function The first 16 links are mapped to the first 16 links of SPE1 and the upper 16 links are mapped to the first 16 links of SPE2. The value of the TS_EN bit in the TRIB_CTL registers will be used to determine tributary to link mapping.
1
8.4.2.2 SBI Link Configuration The AAL1gator-32 supports up to 32 links which, in SBI mode, can be mapped to any tributary on the SBI bus. The lower 16 links and the upper 16 links can be configured as two separate groups to handle 16 E1 or T1 links. Link 0 and link
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16 can alternatively be configured for DS3 mode. A mix of configurations is possible, but all links within the same group have to be configured the same. SBI_LNK_CFG_REG (0x80301) configures the two groups of links in SBI mode. The High group contains the upper 16 links and is configured independently from the low group which contains the bottom 16 links. Per-Group Link Type The LINK_TYPL field defines the link type for the lower group of links. The LINK_TYPH field defines the link type for the higher group of links. If LINK_TYPx is set to E1 or T1 mode, then the T1_MODE bit in the LIN_STR_MODE memory register associated with the links in this group needs to be set to the same value. For example, if LINK_TYPH is set to T1 mode then T1_MODE bit must be set in the LIN_STR_MODE register for links 16-31 (lines 0-7 in both A1SP 2 and A1SP 3). If the LINK_TYPx is set to DS3 mode, then the UDF_HS mode bit should be set in the HS_LIN_REG memory register in either A1SP0 or A1SP2. The encoding of these fields is as follows: Payload Type T1 E1 DS3 Reserved LINK_TYPx[1:0] b"00" b"01" b"10" b"11" T1_MODE 1 0 UDF_HS 0 0 1
Note: The T1_MODE bit is selectable for DS3 payload types as described in section 8.6.1.2. All configurable features covered in section 8.6 for high speed lines is applicable for DS3 links conveyed via SBI. DS3 Fast Clock Generation It is strongly recommended that the DS3 clock be passed externally to the AAL1gator-32. However, DS3 links may use a separate clock input, FASTCLK, for clock generation. The use of FASTCLK will adversely affect jitter performance. Three different FASTCLK frequencies are supported in each case. The FST_CK_FRQL field selects the frequency being used for link number 0. The
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FST_CK_FRQH field selects the frequency being used for link number 16. The encoding of FST_CK_FRQx is given below: FST_CK_FRQx [1:0] "00" "01" "10" "11" FASTCLK Frequency 51.84 MHz 44.928 MHz Reserved 66 MHz
Note: Illegal values on FST_CK_FRQx[1:0] will result in the default frequency of 51.84MHz being used. Clock Kill The CKOUT_KILLL field is used to disable the clock on all the lower 16 links. The CKOUT_KILLH field is used to disable the clock on all the upper 16 links. CKOUT_KILLx 0 1 8.4.2.3 SBI Link Disable The Link Disable n (LINK_DISn) bit allows individual serial SBI local links to be disabled. LINK_DIS[15:0] is located in SBI_LINK_DIS_REGL (0x80302) while LINK_DIS[31:16] is located in SBI_LINK_DIS_REGH (0x80303). All serial links default to being enabled. LINK_DISn 0 1 Link n is enabled. Link n is disabled. Function Clocks are disabled. Function Clocks are not disabled.
8.4.2.4 Synchronous/Asynchronous Mode for Local Links The SYNC Link n (SYNC_LINKn) bit must be set if the SBI local link is mapped to an SBI tributary which is operating in synchronous mode. An SBI tributary is in
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synchronous mode when either the corresponding SPEn_SYNCH is set in the SBI_BUS_CFG register or TRIB_SYNCH is set in the corresponding Insert Tributary Control Register. SYNC_LINK[15:0] is located in SBI_SYNC_LINK_REGL (0x80304) while SYNC_LINK[31:16] is located in SBI_SYNC_LINK_REGH (0x80305). SYNC_LINKn 0 Function Link n is operating in asynchronous mode. The serial clock output to link n will be sourced from the PISO block. Link n is operating in synchronous mode. The serial clock output to link n will be sourced from the Insert SBI Block.
1
In synchronous mode, transmit frame/multi-frame pulses are sourced by the INSBI block. In asynchronous mode, transmit frame/multi-frame pulses are sourced from the SBI tributaries. Therefore, GEN_SYNC in the LIN_STR_MODE memory register must be set to `0'. 8.4.2.5 SBI Alarm Configuration SBI Extract Alarm State Transition Indication When set, SBI_ALRM_INTn indicates that the SBI alarm state has changed on the SBI tributary mapped to this link. This bit is cleared upon reading. Read SBI_ALRM_STATL to see the current state. When a bit is set in either EXT_ALRM_INTL or EXT_ALRM_INTH and SBI_ALARM is enabled, the SBI_ALARM bit will be set in the MSTR_INTR register, which will activate INTB. SBI_ALRM_INT[15:0] is located in EXT_ALRM_INT_REGL (0x80308) and SBI_ALRM_INT[31:16] is located in EXT_ALRM_INT_REGH (0x80309). SBI Extract Alarm Status SBI_ALRM_STATn indicates the current state of the Extract SBI ALARM signal on the SBI tributary mapped to this link. The SBI_ALRM_INTn bit will be set in the SBI_ALRM_INTL or SBI_ALRM_INTH register whenever this bit changes. SBI_ALRM_STAT[15:0] is located in EXT_ALRM_STAT_REGL (0x8030A) and SBI_ALRM_STAT[31:16] is located in EXT_ALRM_STAT_REGH (0x8030B).
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SBI_ALRM_STATn 0 1
Function The ALARM signal for the SBI tributary mapped to link n is not active. The ALARM signal for the SBI tributary mapped to link n is active.
SBI Insert Alarm Indicator Activation When set, the SBI_ALRM_INSn bit will activate the Insert SBI Alarm indicator for the tributary mapped to this link. SBI_ALRM_INS[15:0] is located in INS_ALRM_REGL (0x8030C) and SBI_ALRM_INS[31:16] is located in INS_ALRM_REGH (0x8030D). 8.4.3 Extract SBI Block Configuration The EXSBI demaps up to 32 T1 links, 32 E1 links, two DS3 links from the SBI shared bus. The T1/E1 links can be unframed or framed and channelized, with or without CAS support. The DS3 link can also be unframed or framed. The links, which the EXSBI processes can originate from any SPE but all links within the SPE must be of the same type. Note that link/tributary numbering starts from `1' in SBI mode. EXSBI configuration is performed by programming bits within the following internal registers: Table 13 - EXSBI Block Register Memory Map Offset Register Description Register Mnemonic
These registers are selected when the address = 0x804XX. 0x00 0x01 0x02 0x03 0x04 Extract Control Register Extract FIFO Under Run Interrupt Status Register Extract FIFO Over Run Interrupt Status Register Extract Tributary RAM Indirect Access Address Register Extract Tributary RAM Indirect Access Control Register EXT_CTL EXT_FI_URI EXT_FI_ORI EXT_TRIAD EXT_TRIAC
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0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Extract Tributary Mapping RAM Indirect Access Data Register Extract Tributary Control RAM Indirect Access Data Register SBI Parity Error Interrupt Status Register MIN_DEPTH for T1 and E1 Register MIN_DEPTH for DS3 Register T1 Threshold Register E1 Threshold Register DS3 Threshold Register Reserved Depth Check Reset Interrupt Status Register Extract Master Interrupt Register
EXT_TRIB_MAP EXT_TRIB_CTL SBI_PERR EXT_MD_T1E1 EXT_MD_DS3 EXT_T1_THR EXT_E1_THR EXT_DS3_THR -EXT_DCR_INT EXT_MSTR_INT
8.4.3.1 SBI Extract Control The SBI Extract block is controlled by programming bits within the EXT_CTL (0x80400) register. The default configuration is as follows: Bit SBI_PAR_CTL TS_EN Register Extract Control Register (0x80400) Extract Control Register (0x80400) Value 1 0 0 0 0 0 1 0
SBI_PERR_EN Extract Control Register (0x80400) FIFO_UDR_EN Extract Control Register (0x80400) FIFO_OVR_EN Extract Control Register (0x80400) SYNC_INT_EN Extract Control Register (0x80400) DC_EN APAGE Extract Control Register (0x80400) Extract Control Register (0x80400)
The default indicates that odd parity mode is used for checking the SBI parity signal, all EXSBI interrupts are disabled, tributary to link mapping is disabled, depth check logic is enabled, and page 0 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator-32 links.
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SBI Parity Mode The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI parity signal, DDP, as follows: SBI_PAR_CTL 0 1 Even parity checking. Odd parity checking. Function
Extract SBI Interrupt Enables There are four interrupt enable bits which are used to enable the generation of an interrupt or set of interrupts when the corresponding interrupt condition is detected. When the interrupt enable bit is `0', the corresponding interrupt is disabled. When the interrupt enable bit is `1', the corresponding interrupt is enabled. Interrupt Enable Bit SBI_PERR_EN FIFO_UDR_EN FIFO_OVR_EN SYNC_INT_EN SBI Parity Error FIFO underrun FIFO overrun Depth Check sync error, C1FP sync error, or SBIIP sync error Interrupt Condition
Note: Regardless of whether SBI Parity Error interrupts are enabled or disabled, the SBI Parity checker logic will update the SBI Parity Error Interrupt Status Register (0x80407). One to One Tributary to Link Mapping The TS_EN bit is used to enable the SBI tributary to SBIIP link mapping capability when the TS_EN bit in the SBI_BUS_CFG_REG also enables mapping. TS_EN 0 Function Mapping will be fixed to a one to one mapping and will not be programmable.
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TS_EN 1
Function SBI tributary to local link mapping is enabled and is specified by the contents of the Extract Tributary Mapping Register RAM when TS_EN in SBI_BUS_CFG_REG is also set.
Depth Check Logic This bit enables the Depth Check Logic and is encoded as follows: DC_EN 0 1 Function Depth checker logic is disabled. The depth checker logic will periodically monitor the Data/Framing FIFO Depth and compare it against the write and read pointers. If there is a discrepancy the tributary is synchronously reset by the depth checker.
Note: When in synchronous mode, the DC_EN bit must be clear. Active Page Selection The tributary mapping and control configuration RAMs active page select bit (APAGE) controls the selection of one of two pages in the tributary mapping and control configuration RAMs to be the active page. Changes of the active page as a result of write accesses to APAGE will be synchronized to SBI multi-frame boundaries at C1FP. APAGE 0 Function The configuration in page 0 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator links. The configuration in page 1 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator links.
1
8.4.3.2 SBI Extract Tributary Configuration SBI Extract tributary configuration information is read from and written to the SBI Extract tributary mapping and control RAM.
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Please note that the BUSY bit in the Extract Tributary RAM Indirect Access Control Register (0x80404) might not be cleared for up to 4.32 s after either a mapping page switch or a Control RAM or Mapping RAM access. 8.4.3.2.1 SBI Extract Tributary Mapping Configuration The default tributary to link mapping is straight through i.e. 1:1. Therefore, Link Group LOW, LINK 1 inside the AAL1gator-32 will be mapped by default to SPE1, LINK 1 on the SBI side and so on up to SPE1, LINK 16. Link Group HIGH, LINK 1 inside the AAL1gator will be mapped by default to SPE2, LINK 1 on the SBI side and so on up to SPE2, LINK 16. Any tributary can be mapped to any link, unless the tributary is configured for DS3. In that case the tributary can only be mapped to link 1 or link 17. Note link numbering starts at `1'. SBI Extract mapping information is read from and written to the SBI Extract tributary mapping RAM. The tributary to link mapping for an SBI tributary in the receive direction is configured using the following procedure: 1. Poll the BUSY bit of the Extract Tributary RAM Indirect Access Control Register (0x80404) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. Specify the tributary to which the mapping register operation will apply to by writing the following register: Bit TRIB[4:0] SPE[1:0] MAP_REG Register Extract Tributary RAM Indirect Access Address Register (0x80403) Extract Tributary RAM Indirect Access Address Register (0x80403) Extract Tributary RAM Indirect Access Address Register (0x80403) Value See below See below 1
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the mapping register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be set to specify that the Extract Tributary Mapping Registers are addressed by the SPE[1:0] and TRIB[4:0] fields. 3. Specify the tributary to link mapping to be written to the tributary mapping RAM by writing the following register:
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Bit LINK[4:0]
Register Extract Tributary Mapping RAM Indirect Access Data Register (0x80405)
Value See below See below See below
LINK_GRP_LOW Extract Tributary Mapping RAM Indirect Access Data Register (0x80405) LINK_GRP_HIGH Extract Tributary Mapping RAM Indirect Access Data Register (0x80405)
The LINK[4:0] and LINK_GRP_LOW/HIGH fields are used to specify which link of which link group within the AAL1gator-32 is mapped to the SBI tributary specified in step 2. LINK_GRP_LOW/HIGH specifies the link group while LINK[4:0] specifies the link number. Legal values for LINK[4:0] are b"00001" through b"10000". 4. Trigger an indirect write operation on the tributary mapping RAM by writing the following register: Bit PAGE RWB Register Extract Tributary RAM Indirect Access Control Register (0x80404) Extract Tributary RAM Indirect Access Control Register (0x80404) Value See below 0
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary mapping configuration RAM. Note that the BUSY and HST_ADDR_ERR bits in the Extract Tributary RAM Indirect Access Control Register (0x80404) are read only and are not affected by write operations. Notes: * * * Following a configuration change, which generates a Configuration Reset, a tributary may not become active for up to 1 ms following the change. Mapping of more than one tributary to a link or more than one link to a tributary is not allowed. The mapping RAM only needs to be configured if tributary mapping is enabled (TS_EN='1'). If tributary mapping is disabled, the default 1:1 mapping is automatically assumed and no mapping RAM configuration is necessary.
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* *
Configuration changes should be done while the tributary is disabled. Whether tributary mapping is performed or using default 1:1 mapping, the control RAM needs to be configured for any active tributaries. All tributaries are initialized to being disabled. SBI Extract Tributary Control Configuration
8.4.3.2.2
SBI Extract tributary control information is read from and written to the SBI Extract tributary control RAM. The default configuration of each tributary is as follows: Bit TRIB_ENBL Reserved TRIB_TYP[1:0] CLK_MSTR Register Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Value 0 0 00 0 00
CLK_MODE[1:0] Extract Tributary Control RAM Indirect Access Data Register (0x80406)
In the default state, the tributary is disabled, the tributary type is Structured with CAS, the tributary is a clock slave, and EXT_CKCTL[1:0] is used for clocking. The tributary control information for an SBI tributary in the receive direction is configured using the following procedure: 1. Poll the BUSY bit of the Extract Tributary RAM Indirect Access Control Register (0x80404) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. Specify the tributary to which the control register operation will apply to by writing the following register: Bit TRIB[4:0] Register Extract Tributary RAM Indirect Access Address Register (0x80403) Value See below
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Bit SPE[1:0] MAP_REG
Register Extract Tributary RAM Indirect Access Address Register (0x80403) Extract Tributary RAM Indirect Access Address Register (0x80403)
Value See below 0
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the control register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be cleared to specify that the Extract Tributary Control Registers are addressed by the SPE[1:0] and TRIB[4:0] fields. 3. Specify the configuration data to be written to the tributary control RAM by writing the following register: Bit TRIB_ENBL Reserved TRIB_TYP[1:0] CLK_MSTR CLK_MODE[1:0] Register Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Extract Tributary Control RAM Indirect Access Data Register (0x80406) Value See below 0 See below See below See below
The TRIB_ENBL bit is used to enable the tributary. Writing to the tributary control RAM with the TRIB_ENBL bit set enables the EXSBI to take data from an SBI tributary and transmit that data to the local link mapped to that tributary. The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in the table below. TRIB_TYP should correspond with the FR_STRUCT setting in the LIN_STR_MODE memory register for the link associated with this tributary in the AAL1gator-32 line setup.
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CAS Enabled True False False False Notes: * * * *
Framed
Transparent VT TRIB_TYP FR_STRUCT (Floating) False False False True 00 01 10 11 11 01 10
Description
True True False False
Structured with CAS Structured without CAS Unstructured Transparent VT (not supported)
CAS can only be enabled for a Structured (framed) tributary. "Framed" means framing information available - may be channelized or unchannelized. "Unframed" means no framing information available. If a mixture of CAS and non-CAS connections are being made on the same line, then put the line in Structured with CAS mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for the connections not carrying CAS.
The CLK_MSTR bit is used to specify whether the tributary is a clock master or a clock slave. Setting CLK_MSTR will configure the tributary to be a clock master and clearing CLK_MSTR will configure the tributary to be clock slave. The CLK_MSTR configuration bits are ORed with the CLK_MSTR bit in the SBI_BUS_CFG_REG to allow the chip level to force master mode for all tributaries. When in clock slave mode, the CLK_MODE[1:0] field determines what type of clocking is used for the tributary. CLK_MOD[1:0] is used directly as the CLK_MODE bits of the EXT_LINKRATE output of the Extract TSB. Phase mode is recommended. CLK_MODE is encoded as follows: CLK_MODE[1:0] 00 Use EXT_CKCTL[1:0] Function
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CLK_MODE[1:0] 01 10 11
Function Use only ClkRate field of EXT_LINKRATE Use only Phase field of EXT_LINKRATE Reserved
4. Trigger an indirect write operation on the tributary mapping RAM by writing the following register: Bit PAGE RWB Register Extract Tributary RAM Indirect Access Control Register (0x80404) Extract Tributary RAM Indirect Access Control Register (0x80404) Value See below 0
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary control configuration RAM. Note that the BUSY and HST_ADDR_ERR bits in the Extract Tributary RAM Indirect Access Control Register (0x80404) are read only and are not affected by write operations. Notes: * * Following a configuration change, which generates a Configuration Reset, a tributary may not become active for up to 1 ms following the change. Any write to a Tributary Control register for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control register is unchanged from the previous value.
8.4.3.2.3 SBI Extract Tributary Configuration Read Procedure The SBI tributary mapping and control configuration in the receive direction can be read using the following procedure: 1. Poll the BUSY bit of the Extract Tributary RAM Indirect Access Control Register (0x80404) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started.
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2. Specify the tributary to which the mapping register operation will apply to by writing the following register: Bit TRIB[4:0] SPE[1:0] MAP_REG Register Extract Tributary RAM Indirect Access Address Register (0x80403) Extract Tributary RAM Indirect Access Address Register (0x80403) Extract Tributary RAM Indirect Access Address Register (0x80403) Value See below See below See below
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the mapping register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be cleared to specify that the Extract Tributary Control Registers are addressed and needs to be set to specify that the Extract Tributary Mapping Registers are addressed. 3. Trigger an indirect read operation on the tributary mapping or control RAM by writing the following register: Bit PAGE RWB Register Extract Tributary RAM Indirect Access Control Register (0x80404) Extract Tributary RAM Indirect Access Control Register (0x80404) Value See below 1
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary mapping or control configuration RAMs. Note that the BUSY and HST_ADDR_ERR bits in the Extract Tributary RAM Indirect Access Control Register (0x80404) are read only and are not affected by write operations. 4. Poll the BUSY bit of the Extract Tributary RAM Indirect Access Control Register (0x80404) until it is zero. When BUSY is polled to be zero, data from an indirect read operation is available in either the Extract Tributary Mapping RAM Indirect Access Data Register (0x80405) or the Extract Tributary Control RAM Indirect Access Data Register (0x80406) depending on the value of MAP_REG from step 2.
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5. Read the HST_ADDR_ERR bit of the Extract Tributary RAM Indirect Access Control Register (0x80404). A value of HST_ADDR_ERR = `1' indicates that an illegal host access was attempted. An illegal host access occurs when an attempt is made to access an out of range tributary. This bit is cleared upon a read access. 8.4.3.3 Depth and Threshold Values The following fields are used to modify the minimum depth (MIN_DEP), minimum threshold (MIN_THR) and maximum threshold (MAX_THR) for T1, E1, and DS3 tributaries. These values should remain at their default settings. Bits MIN_DEP_T1[3:0] MIN_DEP_E1[3:0] MIN_DEP_DS3[3:0] Reserved[3:0] MAX_THR_T1[3:0] MIN_THR_T1[3:0] MAX_THR_E1[3:0] MIN_THR_E1[3:0] MAX_THR_DS3[3:0] MIN_THR_DS3[3:0] 8.4.3.4 Extract SBI Interrupts The following master interrupt status bits should be read to detect interrupt conditions in the Extract SBI block: Bit EXT_C1FP_INT EXT_SYNC_INT EXT_FIFO_OVR_INT Register Extract Master Interrupt Status Register (0x8040F) Extract Master Interrupt Status Register (0x8040F) Extract Master Interrupt Status Register (0x8040F) Register MIN_DEPTH for T1 and E1 Register (0x80408) MIN_DEPTH for T1 and E1 Register (0x80408) MIN_DEPTH for DS3 Register (0x80409) MIN_DEPTH for DS3 Register (0x80409) T1 Threshold Register (0x8040A) T1 Threshold Register (0x8040A) E1 Threshold Register (0x8040B) E1 Threshold Register (0x8040B) DS3 Threshold Register (0x8040C) DS3 Threshold Register (0x8040C) Default 0x7 0x7 0x4 0x6 0xD 0x2 0xD 0x2 0xD 0x2
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Bit EXT_FIFO_UDR_INT EXT_SBI_PERR_INT EXT_DC_INT C1FP Realignment
Register Extract Master Interrupt Status Register (0x8040F) Extract Master Interrupt Status Register (0x8040F) Extract Master Interrupt Status Register (0x8040F)
EXT_C1FP_INT is set when a C1FP realignment has been detected. This bit will not be set if SYNC_INT_EN is low in the EXT_CTL register (0x80400). This bit is cleared upon a read access. SBIIP_SYNC Realignment EXT_SYNC_INT is set when a SBIIP_SYNC realignment has been detected. This bit will not be set if SYNC_INT_EN is low in the EXT_CTL register (0x80400). This bit is cleared upon a read access. FIFO Overrun EXT_FIFO_OVR_INT is set when a FIFO Overrun Interrupt is pending. This bit will not be set if FIFO_OVR_EN is low in the EXT_CTL register (0x80400). The FIFO_OVRI bit of the Extract FIFO Overrun Interrupt Status Register (0x80402) is also set when a FIFO overrun is detected and is cleared upon a read access. Only one error can be reported at a time. However errors are latched internally so that if multiple errors occur, any pending errors will be reported when the first one is cleared. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Extract FIFO Overrun Interrupt Status Register (0x80402) are used to specify which link of which Link Group was associated with the FIFO buffer in which the overrun was detected. FIFO Underrun EXT_FIFO_UDR_INT is set when a FIFO Underrun Interrupt is pending. This bit will not be set if FIFO_UDR_EN is low in the EXT_CTL register (0x80400). The FIFO_UDRI bit of the Extract FIFO Underrun Interrupt Status Register (0x80401) is also set when a FIFO underrun is detected and is cleared upon a read access. Only one error can be reported at a time. However errors
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are latched internally so that if multiple errors occur, any pending errors will be reported when the first one is cleared. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Extract FIFO Underrun Interrupt Status Register (0x80401) are used to specify which link of which Link Group was associated with the FIFO buffer in which the underrun was detected. SBI Parity Error EXT_SBI_PERR_INT is set when a SBI Parity Error Interrupt is pending. This bit will not be set if SBI_PERR_EN is low in the EXT_CTL register (0x80400). The PERRI bit of the SBI Parity Error Interrupt Status Register (0x80407) is also set when an SBI parity error has been detected and is cleared upon a read access. The TRIB[4:0] and SPE[1:0] fields of the SBI Parity Error Interrupt Status Register (0x80407) are used to specify the SBI tributary for which a parity error was detected. These fields are only valid only when PERRI is set. Depth Check Error EXT_DC_INT is set when an Extract Depth Check Interrupt is pending. his bit will not be set if SYNC_INT_EN is low in the EXT_CTL register (0x80400). The DCR_INTI bit of the Extract Depth Check Interrupt Status Register (0x8040E) is also set when a Depth Check error is detected and is cleared upon a read access. This error is detected when the internal FIFO pointers do match the expected internal FIFO depth. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Extract Depth Check Interrupt Status Register (0x8040E) are used to specify which link of which Link Group was associated with Depth Check error. These fields are only valid when DCR_INTI is set. 8.4.4 Insert SBI Block Configuration The INSBI maps up to 32 T1 or E1 links, or two DS3 links to the SBI shared bus. The T1/E1 links can be unframed or framed and channelized, with or without CAS support. The DS3 link can also be unframed or framed. The links which the INSBI processes can be mapped into any tributary in any SPE but all tributaries within an SPE must be all of the same type. Note that link/tributary numbering starts from `1' in SBI mode.
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INSBI configuration is performed by programming bits within the following internal registers: Table 14 - INSBI Block Register Memory Map Offset Register Description Register Mnemonic
These registers are selected when the address = 0x805XX. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 Insert Control Register Insert FIFO Underrun Interrupt Status Register Insert FIFO Overrun Interrupt Status Register Insert Tributary Register Indirect Access Address Register Insert Tributary Register Indirect Access Control Register Insert Tributary Mapping Register Indirect Access Data Register Insert Tributary Control Register Indirect Access Data Register MIN_DEPTH for T1 and E1 Register MIN_DEPTH for DS3 Register MIN_THR and MAX_THR for T1 Register MIN_THR and MAX_THR for E1 Register MIN_THR and MAX_THR for DS3 Register Reserved Reserved Reserved Reserved Reserved Depth Check Reset Interrupt Status Register Insert Master Interrupt Register INS_DCR_INT INS_MSTR_INT INS_CTL INS_FI_URI INS_FI_ORI INS_TRIAD INS_TRIAC INS_TRIB_MAP INS_TRIB_CTL INS_MD_T1E1 INS_MD_DS3 INS_THR_T1 INS_THR_E1 INS_THR_DS3
8.4.4.1 SBI Insert Control The SBI Insert block is controlled by programming bits within the INS_CTL (0x80500) register. The default configuration is as follows:
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Bit SBI_PAR_CTL TS_EN
Register Insert Control Register (0x80500) Insert Control Register (0x80500)
Value 1 0 0 0 0 1 0
FIFO_UDR_EN Insert Control Register (0x80500) FIFO_OVR_EN Insert Control Register (0x80500) SYNC_INT_EN Insert Control Register (0x80500) DC_EN APAGE Insert Control Register (0x80500) Insert Control Register (0x80500)
The default indicates that odd parity mode is used for checking the SBI parity signal, all INSBI interrupts are disabled, tributary to link mapping is disabled, depth check logic is enabled, and page 0 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator-32 links. SBI Parity Mode The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI data parity signal, ADP, as follows: SBI_PAR_CTL 0 1 Even parity generation. Odd parity generation. Function
One to One Tributary to Link Mapping The TS_EN bit is used to enable the SBI tributary to AAL1gator link mapping capability when the TS_EN bit in the SBI_BUS_CFG_REG also enables mapping. TS_EN 0 Function Mapping will be fixed to a one to one mapping and will not be programmable.
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TS_EN 1
Function SBI tributary to AAL1gator link mapping is enabled and is specified by the contents of the Insert Tributary Mapping Register RAM when TS_EN in SBI_BUS_CFG_REG is also set.
Insert SBI Interrupt Enables There are three interrupt enable bits which are used to enable the generation of an interrupt or set of interrupts when the corresponding interrupt condition is detected. When the interrupt enable bit is `0', the corresponding interrupt is disabled. When the interrupt enable bit is `1', the corresponding interrupt is enabled. Interrupt Enable Bit FIFO_UDR_EN FIFO_OVR_EN SYNC_INT_EN Depth Check Logic This bit enables the Depth Check Logic and is encoded as follows: DC_EN 0 1 Function Depth checker logic is disabled. The depth checker logic will periodically monitor the Data/Framing FIFO Depth and compare it against the write and read pointers. If there is a discrepancy the tributary is synchronously reset by the depth checker. FIFO underrun FIFO overrun Depth Check sync error, C1FP sync error, or SBIIP sync error Interrupt Condition
Note: When in synchronous mode, the DC_EN bit must be clear. Active Page Selection The tributary mapping and control configuration RAMs active page select bit (APAGE) controls the selection of one of two pages in the tributary mapping and control configuration RAMs to be the active page. Changes of the active page
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as a result of write accesses to APAGE will be synchronized to SBI multi-frame boundaries at C1FP. APAGE 0 Function The configuration in page 0 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator links. The configuration in page 1 of the tributary mapping and control configuration RAMs is used to associate incoming tributaries to AAL1gator links.
1
8.4.4.2 SBI Insert Tributary Configuration SBI Insert tributary configuration information is read from and written to the SBI Insert tributary mapping and control RAM. Please note that the BUSY bit in the Extract Tributary RAM Indirect Access Control Register (0x80404) might not be cleared for up to 4.32 s after either a mapping page switch or a Control RAM or Mapping RAM access. 8.4.4.2.1 SBI Insert Tributary Mapping Configuration The default tributary to link mapping is straight through i.e. 1:1. Therefore, Link Group LOW, LINK 1 inside the AAL1gator-32 will be mapped by default to SPE1, LINK 1 on the SBI side and so on up to SPE1, LINK 16. Link Group HIGH, LINK 1 inside the AAL1gator will be mapped by default to SPE2, LINK 1 on the SBI side and so on up to SPE2, LINK 16. Any tributary can be mapped to any link, unless the tributary is configured for DS3. In that case the tributary can only be mapped to link 1 or link 17. Please note that link numbering starts at `1'. SBI Insert mapping information is read from and written to the SBI Insert tributary mapping RAM. The tributary to link mapping for an SBI tributary in the transmit direction is configured using the following procedure: 1. Poll the BUSY bit of the Insert Tributary RAM Indirect Access Control Register (0x80504) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. Specify the tributary to which the mapping register operation will apply to by writing the following register:
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Bit TRIB[4:0] SPE[1:0] MAP_REG
Register Insert Tributary RAM Indirect Access Address Register (0x80503) Insert Tributary RAM Indirect Access Address Register (0x80503) Insert Tributary RAM Indirect Access Address Register (0x80503)
Value See below See below 1
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the mapping register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be set to specify that the Insert Tributary Mapping Registers are addressed by the SPE[1:0] and TRIB[4:0] fields. 3. Specify the tributary to link mapping to be written to the tributary mapping RAM by writing the following register: Bit LINK[4:0] Register Insert Tributary Mapping RAM Indirect Access Data Register (0x80505) Value See below See below See below
LINK_GRP_LOW Insert Tributary Mapping RAM Indirect Access Data Register (0x80505) LINK_GRP_HIGH Insert Tributary Mapping RAM Indirect Access Data Register (0x80505)
The LINK[4:0] and LINK_GRP_LOW/HIGH fields are used to specify which link of which link group within the AAL1gator is mapped to the SBI tributary specified in step 2. LINK_GRP_LOW/HIGH specifies the link group while LINK[4:0] specifies the link number. Legal values for LINK[4:0] are b"00001" through b"10000". 4. Trigger an indirect write operation on the tributary mapping RAM by writing the following register: Bit PAGE Register Insert Tributary RAM Indirect Access Control Register (0x80504) Value See below
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Bit RWB
Register Insert Tributary RAM Indirect Access Control Register (0x80504)
Value 0
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary mapping configuration RAM. Note that the BUSY and HST_ADDR_ERR bits in the Insert Tributary RAM Indirect Access Control Register (0x80504) are read only and are not affected by write operations. Notes: * * * Following a configuration change, which generates a Configuration Reset, a tributary may not become active for up to 1 ms following the change. Mapping of more than one tributary to a link or more than one link to a tributary is not allowed. Whether tributary mapping is performed or default 1:1 mapping is used, the above steps must be done and must be repeated for every tributary access.
8.4.4.2.2 SBI Insert Tributary Control Configuration SBI Insert tributary control information is read from and written to the SBI Insert tributary control RAM. The default configuration of each tributary is as follows: Bit TRIB_ENBL TRIB_TYP[1:0] CLK_MSTR SYNCH_TRIB Register Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Value 0 00 0 0
In the default state, the tributary is disabled, the tributary type is Structured with CAS, the tributary is a clock slave, and the tributary is free to float (i.e. - is in asynchronous mode).
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The tributary control information for an SBI tributary in the receive direction is configured using the following procedure: 1. Poll the BUSY bit of the Insert Tributary RAM Indirect Access Control Register (0x80504) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. Specify the tributary to which the control register operation will apply to by writing the following register: Bit TRIB[4:0] SPE[1:0] MAP_REG Register Insert Tributary RAM Indirect Access Address Register (0x80503) Insert Tributary RAM Indirect Access Address Register (0x80503) Insert Tributary RAM Indirect Access Address Register (0x80503) Value See below See below 0
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the control register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be cleared to specify that the Insert Tributary Control Registers are addressed by the SPE[1:0] and TRIB[4:0] fields. 3. Specify the configuration data to be written to the tributary control RAM by writing the following register: Bit TRIB_ENBL TRIB_TYP[1:0] CLK_MSTR SYNCH_TRIB Register Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Insert Tributary Control RAM Indirect Access Data Register (0x80506) Value See below See below See below See below
The TRIB_ENBL bit is used to enable the tributary. Writing to the tributary control RAM with the TRIB_ENBL bit set enables the INSBI to take tributary
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data from an AAL1gator link and transmit that data to the SBI tributary mapped to that link. The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in the table below. TRIB_TYP should correspond with the FR_STRUCT setting in the LIN_STR_MODE memory register for the link associated with this tributary in the AAL1gator-32 line setup. CAS Enabled True False False False Notes: * * * * CAS can only be enabled for a Structured (framed) tributary. "Framed" means framing information available - may be channelized or unchannelized. "Unframed" means no framing information available. If a mixture of CAS and non-CAS connections are being made on the same line, then put the line in Structured with CAS mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for the connections not carrying CAS. Framed Transparent VT TRIB_TYP FR_STRUCT (Floating) False False False True 00 01 10 11 11 01 10 Description
True True False False
Structured with CAS Structured without CAS Unstructured Transparent VT (not supported)
The CLK_MSTR bit is used to specify whether the tributary is a clock master or a clock slave. Setting CLK_MSTR will configure the tributary to be a clock master and clearing CLK_MSTR will configure the tributary to be clock slave. The CLK_MSTR configuration bits are ORed with the CLK_MSTR bit in the SBI_BUS_CFG_REG to allow the chip level to force master mode for all tributaries. The SYNCH_TRIB bit is used to indicate whether the tributary is locked to the SBI SPE (i.e. - is in synchronous mode). If this bit is set than the tributary is
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locked. If this bit is not set, then the tributary is free to float (i.e. - is in asynchronous mode). 4. Trigger an indirect write operation on the tributary mapping RAM by writing the following register: Bit PAGE RWB Register Insert Tributary RAM Indirect Access Control Register (0x80504) Insert Tributary RAM Indirect Access Control Register (0x80504) Value See below 0
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary control configuration RAM. Note that the BUSY and HST_ADDR_ERR bits in the Insert Tributary RAM Indirect Access Control Register (0x80504) are read only and are not affected by write operations. Notes: * * Following a configuration change, which generates a Configuration Reset, a tributary may not become active for up to 1 ms following the change. Any write to a Tributary Control register for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control register is unchanged from the previous value.
8.4.4.2.3 SBI Insert Tributary Configuration Read Procedure The SBI tributary mapping and control configuration in the receive direction can be read using the following procedure: 1. Poll the BUSY bit of the Insert Tributary RAM Indirect Access Control Register (0x80504) until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. Specify the tributary to which the mapping register operation will apply to by writing the following register: Bit TRIB[4:0] Register Insert Tributary RAM Indirect Access Address Register (0x80503) Value See below
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Bit SPE[1:0] MAP_REG
Register Insert Tributary RAM Indirect Access Address Register (0x80503) Insert Tributary RAM Indirect Access Address Register (0x80503)
Value See below See below
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the mapping register write operation will apply to. Legal values for TRIB[4:0] are b"00001" through b"11100". Legal values for SPE[1:0] are b"01" through b"11". The MAP_REG bit needs to be cleared to specify that the Insert Tributary Control Registers are addressed and needs to be set to specify that the Insert Tributary Mapping Registers are addressed. 3. Trigger an indirect read operation on the tributary mapping or control RAM by writing the following register: Bit PAGE RWB Register Insert Tributary RAM Indirect Access Control Register (0x80504) Insert Tributary RAM Indirect Access Control Register (0x80504) Value See below 1
The PAGE bit selects between the two pages (page 0 or page 1) in the tributary mapping or control configuration RAMs. Note that the BUSY and HST_ADDR_ERR bits in the Insert Tributary RAM Indirect Access Control Register (0x80504) are read only and are not affected by write operations. 4. Poll the BUSY bit of the Insert Tributary RAM Indirect Access Control Register (0x80504) until it is zero. When BUSY is polled to be zero, data from an indirect read operation is available in either the Insert Tributary Mapping RAM Indirect Access Data Register (0x80505) or the Insert Tributary Control RAM Indirect Access Data Register (0x80506) depending on the value of MAP_REG from step 2. 5. Read the HST_ADDR_ERR bit of the Insert Tributary RAM Indirect Access Control Register (0x80504). A value of HST_ADDR_ERR = `1' indicates that an illegal host access was attempted. An illegal host access occurs when an attempt is made to access an out of range tributary. This bit is cleared upon a read access.
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8.4.4.3 Depth and Threshold Values The following fields are used to modify the minimum depth (MIN_DEP), minimum threshold (MIN_THR) and maximum threshold (MAX_THR) for T1, E1, and DS3 tributaries. In most cases, these values should remain at their default settings. However, for T1/E1 applications, where the AAL1gator-32 is a clock master, the MAX_THR value should be changed to 0xA. Bits MIN_DEP_T1[3:0] MIN_DEP_E1[3:0] MIN_DEP_DS3[3:0] Reserved[3:0] MAX_THR_T1[3:0] MIN_THR_T1[3:0] MAX_THR_E1[3:0] MIN_THR_E1[3:0] MAX_THR_DS3[3:0] MIN_THR_DS3[3:0] 8.4.4.4 Insert SBI Interrupts The following master interrupt status bits should be read to detect interrupt conditions in the Insert SBI block: Bit EXT_C1FP_INT EXT_SYNC_INT EXT_FIFO_OVR_INT EXT_FIFO_UDR_INT EXT_DC_INT Register Insert Master Interrupt Status Register (0x80512) Insert Master Interrupt Status Register (0x80512) Insert Master Interrupt Status Register (0x80512) Insert Master Interrupt Status Register (0x80512) Insert Master Interrupt Status Register (0x80512) Register MIN_DEPTH for T1 and E1 Register (0x80507) MIN_DEPTH for T1 and E1 Register (0x80507) MIN_DEPTH for DS3 Register (0x80508) MIN_DEPTH for DS3 Register (0x80508) T1 Threshold Register (0x80509) T1 Threshold Register (0x80509) E1 Threshold Register (0x8050A) E1 Threshold Register (0x8050A) DS3 Threshold Register (0x8050B) DS3 Threshold Register (0x8050B) Default 0x7 0x7 0xC 0x0 0xE 0x6 0xE 0x2 0x6 0x8
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C1FP Realignment INS_C1FP_INT is set when a C1FP realignment has been detected. This bit will not be set if SYNC_INT_EN is low in the INS_CTL register (0x80500). This bit is cleared upon a read access. SBIIP_SYNC Realignment INS_SYNC_INT is set when a SBIIP_SYNC realignment has been detected. This is an internal bus error. This bit will not be set if SYNC_INT_EN is low in the INS_CTL register (0x80500). This bit is cleared upon a read access. FIFO Overrun INS_FIFO_OVR_INT is set when a FIFO Overrun Interrupt is pending. This bit will not be set if FIFO_OVR_EN is low in the INS_CTL register (0x80500). The FIFO_OVRI bit of the Insert FIFO Overrun Interrupt Status Register (0x80502) is also set when a FIFO overrun is detected and is cleared upon a read access. Only one error can be reported at a time. However errors are latched internally so that if multiple errors occur, any pending errors will be reported when the first one is cleared. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Insert FIFO Overrun Interrupt Status Register (0x80502) are used to specify which link of which Link Group was associated with the FIFO buffer in which the overrun was detected. FIFO Underrun INS_FIFO_UDR_INT is set when a FIFO Underrun Interrupt is pending. This bit will not be set if FIFO_UDR_EN is low in the INS_CTL register (0x80500). The FIFO_UDRI bit of the Insert FIFO Underrun Interrupt Status Register (0x80501) is also set when a FIFO underrun is detected and is cleared upon a read access. Only one error can be reported at a time. However errors are latched internally so that if multiple errors occur, any pending errors will be reported when the first one is cleared. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Insert FIFO Underrun Interrupt Status Register (0x80501) are used to specify which link of which Link Group was associated with the FIFO buffer in which the underrun was detected.
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Depth Check Error INS_DC_INT is set when an Insert Depth Check Interrupt is pending. This bit will not be set if SYNC_INT_EN is low in the INS_CTL register (0x80500). The DCR_INTI bit of the Insert Depth Check Interrupt Status Register (0x80511) is also set when a Depth Check error is detected and is cleared upon a read access. This error is detected when the internal FIFO pointers do match the expected internal FIFO depth. The LINK[4:0] and LINK_GRP_LOW/HIGH fields of the Insert Depth Check Interrupt Status Register (0x80511) are used to specify which link of which Link Group was associated with Depth Check error. These fields are only valid when DCR_INTI is set. 8.4.5 Line Clock Source Several clocking options exist in this mode and are controlled by the value of the CLK_SOURCE bits in the LIN_STR_MODE register for each line. The CLK_SOURCE bits must be in a compatible setting with respect to the CLK_MSTR setting discussed in sections 8.4.4.2.2 and 8.4.3.2.2. 8.4.5.1 Receive Line Clock Source In the receive direction, the line clock source has two options based on the value of the CLK_SOURCE_RX bit in LIN_STR_MODE. This bit should only be set when supporting DS3 tributaries. CLK_SOURCE_RX 0 1 Function The line receives its clock from the external clock (RL_CLK[n] pin) associated with that line. The line receives its clock from the SBI.
8.4.5.2 Transmit Line Clock Source In the transmit direction, seven possible options exist and are controlled by the value of the CLK_SOURCE_TX bits in the LIN_STR_MODE memory register for each line. This value will override the setting defined by the TLCLK_OE input pin. If switching from an external to an internal clock or visa versa, make sure there are not two clocks driving simultaneously.
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The seven options are listed in the following table. All options but the last require that the AAL1gator is the SBI clock master for that line in the Add direction. CLK_SOURCE_TX[2:0 ] 000 001 010 Function Clock is an input on pin TL_CLK[n]. Clock is an input on pin RL_CLK[n] (loop timing mode). Clock is internally synthesized as a nominal T1 or E1 clock based on SYS_CLK and the value of T1_MODE. The clock is output on the TL_CLK[n] pin. Clock is internally synthesized based on the received SRTS values. The clock is output on TL_CLK[n] pin. Clock is internally synthesized using the adaptive algorithm which uses receive buffer depth to control TL_CLK[n]. The clock is output on TL_CLK[n] pin. Clock is internally synthesized based on values received on the external clock control interface. This mode is used for external implementations of SRTS or Adaptive clocking. The clock is output on TL_CLK[n] pin. Not Valid in SBI mode SBI is clock master, use SBI clock.
011 100
101
110 111
Please see 8.3.2.2.1 for a description of the CGC block which implements internally synthesized clocks. All configurable features in that section are applicable for lines conveyed via SBI with CLK_SOURCE_TX options "010" through "101". 8.4.6 Other Per-Line Options Low CDV for Unstructured Mode For unstructured lines conveyed via SBI, the LOW_CDV bit of the LIN_STR_MODE memory register can be set to cause cells to be scheduled every 47 bytes instead of using frame based scheduling. This eliminates the CDV caused by the scheduler. This mode can only be used in unstuctured mode when BYTES_PER_CELL is 47. This mode cannot be used when the queue is configured for partial cells or for AAL0 mode.
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LOW_CDV 0 1
Function Unstructured line is not in low CDV mode. AAL1gator uses frame based scheduling. Unstructured line is in low CDV mode. AAL1gator uses byte based scheduling where cells are scheduled every 47 bytes.
8.5
H-MVIP Mode The High Speed Multi-Vendor Integration Protocol (H-MVIP) bus provides synchronous, time-division multiplexed transport of N x 64 kbps constant bit rate (CBR) data streams. The H-MVIP bus consists of a group of related clock signals and serial data streams which operate at 8 Mbps. In H-MVIP mode, each incoming external 8 Mbps H-MVIP data stream and breaks it into 4 separate local 2Mbps data streams. The bytes are taken off the bus in round robin fashion and sent to separate 2Mbps links. In the outgoing direction the H-MVIP block takes each group of four 2Mbps local links and combines them into one external 8 Mbps H-MVIP data stream. In H-MVIP mode, there is a common 16 MHz clock, a 4 MHz clock, and a common framing reference signal. Separate data pins and signaling pins are provided in each direction for each line. Individual time slots cannot be disabled. DS1 / E1 Links The AAL1gator-32, AAL1gator-8 and AAL1gator-4 support eight, two and one HMVIP line, respectively, where each H-MVIP line supports four DS1/E1 links each. Each link can be individually configured for either Basic Service (no CAS) or Service with CAS. Structured J2 Links By mapping a J2 frame into an H-MVIP frame, the AAL1gator can circuit emulate individual N x 64 kbps timeslots or groups of timeslots. Note that because the HMVIP data stream is internally divided into 4 separate 2 Mbps streams, groups of timeslots are required to be within a 2 Mbps stream boundary of thirty-two timeslots. The AAL1gator-32, AAL1gator-8 and AAL1gator-4 support eight, two and one Structured J2 Basic Service links respectively.
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8.5.1 Line Format and Frame Structure For H-MVIP mode, the T1_MODE bit in the LIN_STR_MODE register and the MVIP_EN bit in the LS_Ln_CFG_REG should both be low. The frame structure for H-MVIP lines can be Structured Data Format - Frame (SDF-FR) or Structured Data Format - Multiframe (SDF-MF) and is determined by the value of FR_STRUCT[1:0] in the LIN_STR_MODE memory register for each line as follows: FR_STRUCT[1:0] 00 01 10 11 SDF-MF SDF-FR Frame Structure Not Used. A structured connection where CAS signaling is not being transported (basic service). Not valid in H-MVIP mode. A structured connection where CAS signaling is being transported. Description
Note: If a mixture of CAS and non-CAS connections are being made on the same line, then put the line in SDF-MF mode and set R_CHAN_NO_SIG and T_CHAN_NO_SIG in the queue tables for the connections not carrying CAS. 8.5.2 Line Clock Source In H-MVIP mode there is a common 16 Mhz clock (HMVIP16CLK) whose every other rising edge is used to sample data on all external lines in the receive direction and whose every other falling edge is used to source data on all external lines in the transmit direction. There is also a common 4 Mhz clock (HMVIP4CLK) whose falling edge is used to sample the frame pulse. Internally a 2 Mhz clock is generated for each link which connects to the A1SP block(s). Because H-MVIP lines all run off the same clock, there is only one clocking option available in this mode. Therefore the CLK_SOURCE values are not used. The HMVIP16CLK and HMVIP4CLK will always be used and a clock will be expected on these pins. SRTS_EN should stay low in this mode.
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8.5.3 Synchronization A common frame pulse, F0B, is used to indicate the start of a frame for all external lines. Individual local link frame pulses are derived from F0B. This signal is always an input. In H-MVIP mode, synchronization is always controlled from the external interface and the sync signal is always considered to be a frame synchronization signal. Therefore MF_SYNC_MODE and GEN_SYNC should be inactive (stay low) for all lines when this mode is in use. 8.5.4 CAS Signaling Signaling is passed through as received and sent with the corresponding data byte. Signaling format is the same as in Direct Low Speed mode, where the last nibble of each timeslot carries the CAS signaling bits. The E1_WITH_T1_SIG bit in LIN_STR_MODE can be configured in H-MVIP mode. See section 8.3.4 for a detailed discussion of signaling. E1_WITH_T1_SIG is encoded as follows: E1_WITH_T1_SIG 0 1 8.6 High Speed Mode The High Speed Line Interface mode is used to interface to high speed clear channel, unstructured data streams. The Line Interface Block just passes the clock and data between the external lines and the corresponding local link. Only clock and data are used. The data is passed as a clear channel bit stream and data rates are supported up to 45 Mbps. Timing recovery is supported externally. The AAL1gator's External Clock Interface outputs various signals including SRTS and Adaptive Status values. DS3 / E3 / STS-1 / STM-0 Links In High Speed Mode, the AAL1gator-32 supports two DS3 , E3 or STS-1/STM-0 links where external lines 0, and 2 are connected to local links 0 and 16 respectively. Function Use E1 signaling. Signaling is updated every 16 frames. Use T1 signaling. Signaling is updated every 24 frames instead of every 16 frames.
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In High Speed Mode, the AAL1gator-8 and AAL1gator-4 support one DS3 , E3 or STS-1/STM-0 link where external line 0 is connected to local link 0. 8.6.1 High Speed Line Configuration The configuration of the high speed lines is stored in the HS_LIN_REG memory register for the corresponding A1SP. All settings are only applicable to line 0 of the A1SP. For AAL1gator-32, A1SP 0 and A1SP 2 are used for the high speed lines. For AAL1gator-8 and AAL1gator-4, A1SP 0 is used for the high speed line. HS_LIN_REG has the following bit format. Please note that writes to this register will not take into effect until the An_CMDREG_ATTN bit is set in the An_CMD_REG. Table 15 - HS_LIN_REG Format Bit 13:6 5 4 3 Field Initialize to 0. Write with a 0 to maintain future software compatibility. See section 6.6.1.1, Transmit Conditioning. See section 6.6.1.1, Transmit Conditioning. Fetch receive conditioning data from the R_COND_DATA buffer for line 0, channels 0 and 1. High-speed mode (line 0 only). See discussion below. Write with a 0 to maintain future software compatibility. Not used HS_GEN_DS3_AIS HS_TX_COND HS_RX_COND Description
15:14 Reserved
2 1:0
UDF_HS Unused
Line 0 of the A1SP is configured for Unstructured Data Format - High Speed (UDF-HS) mode by setting the UDF_HS bit in HS_LIN_REG. For AAL1gator-32, A1SP0 and A1SP2 need to be configured for UDF-HS mode. For AAL1gator-8 and AAL1gator-4, A1SP 0 needs to be configured for UDF-HS mode. UDF_HS 0 1 Function Disables the UDF-HS (T3/E3/STS-1/STM-0) mode. Enables the UDF-HS (T3/E3/STS-1/STM-0) mode. If this mode is selected, the T_QUEUE_TBL and R_QUEUE_TBL entry index 0 are used.
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8.6.1.1 Transmit Cell Conditioning Under certain alarm conditions such as Loss of Signal (LOS), an Alarm Indication Signal (AIS) needs to be transmitted downstream in the cell transmit direction. This means that cells need to be generated which carry an AIS pattern (conditioned data). For E3 links, this can be done by setting the HS_TX_COND bit in the HS_LIN_REG register. When this bit is set, cells with an all ones pattern will be generated. However, a DS3 AIS signal is a framed "1010" pattern. This signal can be generated by setting the HS_GEN_DS3_AIS bit in the HS_LIN_REG register. 8.6.1.2 Receive Cell Conditioning In High Speed Mode, the HS_RX_COND bit in HS_LIN_REG is set to force the playing out of conditioned data. Also, when no data is present in the VC receive buffer, the AAL1gator declares an underrun condition and automatically plays out conditioned data. In High Speed Mode, the T1_MODE bit in LIN_STR_MODE is used to determine the type of conditioned data being played out in the above two situations: T1_MODE 0 1 Function The conditioned data from the R_COND_DATA buffer for line 0, channels 0 and 1 is played out. The framed DS3 AIS pattern is played out.
Note: There is no old data or pseudorandom data options available for UDF-HS mode. 8.6.2 Line Clock Source 8.6.2.1 Receive Line Clock Source In the receive direction, the line clock source must be the RL_CLK[n] input pin associated with the high speed line. Therefore, CLK_SOURCE_RX must be set to `0'.
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8.6.2.2 Transmit Line Clock Source In the transmit direction, two possible options exist and are controlled by the value of the CLK_SOURCE_TX bits in the LIN_STR_MODE memory register for each line. The options are listed below: CLK_SOURCE_TX[2:0 ] 000 001 Function Clock is an input on pin TL_CLK[n]. Clock is an input on pin RL_CLK[n] (loop timing mode).
8.6.2.2.1 Synchronous Residual Time Stamp SRTS functionality is enabled by setting the SRTS_EN bit in the LIN_STR_MODE memory register. SRTS is supported for unstructured data formats on a per-line basis. SRTS_EN 0 1 Function SRTS disabled. The CSI bits of the odd transmit AAL1 cells are set to `0' and the received SRTS bits are ignored. SRTS enabled. The insertion of the transmit SRTS bits is enabled for this line and the received SRTS bits are accumulated.
8.6.3 Other Per-Line Options By default, a high speed queue is always configured for low CDV and the LOW_CDV bit of the LIN_STR_MODE is ignored.
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9
CONFIGURING THE A1SP BLOCKS The following internal registers are used to configure the A1SP blocks. Please note that only the registers for A1SP 0 are used in the AAL1gator-8 and AAL1gator-4.
9.1
Sending OAM Cells The An_SEND_OAM bits in the A1SPn Command Register (0x80010, ... 13) are used to send OAM cells in the TX OAM buffer as follows: Bit 2 Function Description
An_SEND_OAM_1 A write of 1 causes the cell in the TX OAM buffer 1 for the corresponding A1SP to be sent. Reads as a 0 when the cell has been sent. An_SEND_OAM_0 A write of 1 causes the cell in the TX OAM buffer 0 for the corresponding A1SP to be sent. Reads as a 0 when the cell has been sent.
1
9.2
Adding Queues In order to add a queue the processor has to write the ADDQ_FIFO. The ADDQ_FIFO consists of 64 16-bit entries and is accessed using a single address. The format of the ADDQ_FIFO word is shown in Figure 20. The first byte specifies the number of the queue to be added. The next six bits represent an offset that is used to spread the scheduling of cells across multiple frames. This helps to avoid the problem of clumping, which refers to contention with other cells scheduled during the same frame. The upper bit indicates whether or not the ADDQ_FIFO is empty. This bit can be polled after adding queues to find out when they all have been added. The Empty bit indicates Empty status when it is set. The amount of time it takes to empty the FIFO is dependent on how full it is, whether TALP is processing cells and whether there is back pressure on the UTOPIA bus. ADDQ_FIFO entries can only be processed when TALP is idle. If the TALP_FIFO fills and prevents TALP from processing cells, this will prevent ADDQ_FIFO entries from being processed. Note that the Offset and Queue Number fields are write only and cannot be read. The Empty field is read only and cannot be written.
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Figure 20 - ADDQ_FIFO Word Structure
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Empty
Unused
Offset
Queue Number
Queues are added by writing to the An_ADDQ_FIFO (0x80020, ..., 23) register with the number of the queue to be added. The fields of the An_ADDQ_FIFO register is summarized below: Bit 15 Function EMPTY Description This field indicates when the Add Queue FIFO is empty. It can be polled to determine when the A1SP module has finished processing the ADDQ_FIFO entries that were in the FIFO. This field indicates the offset from the cell scheduling reference value. This offset can be used to spread the scheduling of cells across multiple frames in order to control clumping Note that this field is invalid on reads. The number of the queue being added. Note that this field is invalid on reads.
13:8
OFFSET
7:0 9.3
QUEUE_NUM
A1SP Clock Configuration The A1SPn Clock Configuration Register (0x80030, ... 33) is used to configure the internal adaptive clocking algorithm and the dividing down of the network-derived clock, NCLK, used for SRTS as follows: Bit 9 Function Description
NCLK_DIV_EN When set, the NCLK is divided down as specified by the NCLK_DIV field. Otherwise the NCLK is passed directly from the NCLK pin to this A1SP. NCLK_DIV When NCLK_DIV_EN is set, this field indicates how much to divide down the NCLK for this A1SP. The clock is divided by ((NCLK_DIV + 1) *2). This field is "0000" by default so the NCLK is divided by 2. If this field is "1111" then NCLK is divided by 32.
8:5
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Bit 4:0
Function ADAP_FILT_ SIZE
Description When a line is configured to use the internal adaptive clocking algorithm, this field defines the size of the filtering window. The filter size is a power of 2 where ADAP_FILT_SIZE represents the exponent (i.e. 2ADAP_FILT_SIZE). The adaptive algorithm determines the clock frequency by averaging the byte difference over 2ADAP_FILT_SIZE number of samples. The maximum value is "10000" or 16. The default value is 200000B = 1.
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10
CONFIGURING THE RAM INTERFACE The AAL1gator has a separate SRAM and processor interface. The RAM Interface is the central arbiter for all memory accesses. It provides a priority mechanism that incorporates fairness to satisfy all real-time requirements of the various blocks. All blocks requesting a data transfer with the common memory supply the address, control signals, and the data, if the requested data transfer is a write, to the RAMI. When the RAMI actually grants the transfer, it provides a grant signal to the requesting block, indicating that the transfer has been performed. The memory is arbitrated on a cycle-by-cycle basis. No device is granted the bus for an indefinite time. For the AAL1gator-32, either one or two external 256K x 16 or 256K x 18 (10 ns) SRAMs are needed, depending on the mode of operation. Two rams are required if the AAL1gator-32 is configured to use the SBI interface, the upper four 8 Mbps MVIP interfaces, or the upper two High speed interfaces. For the AAL1gator-8 and the AAL1gator-4, one external 128K x 16 or 128K x 18 (10 ns) SRAM is needed. The SRAM interface runs at the same frequency as SYS_CLK and can run up to 45 Mhz. The RAM interface is configured in the RAM Configuration Register (0x80100). The default configuration indicates use of pipelined SSRAM protocol and odd parity generation/checking for the RAM interfaces: Bit RAM_EVEN_PAR SRAM Selection Either a synchronous SRAM with a single cycle deselect or a pipelined ZBT or ZBT compatible SRAM can be used. For most applications the synchronous SRAM is sufficient, but if additional performance is needed, such as in cross connect applications which need to use partial cells to lower delay, the ZBT ram is recommended. The SSRAM_ZBT_MODE bit selects between SSRAM and ZBT SRAM: Register Value 0 0
SSRAM_ZBT_MODE RAM Configuration Register (0x80100) RAM Configuration Register (0x80100)
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SSRAM_ZBT_MODE 0
Function The pipelined SSRAM protocol is used on the RAM interfaces allowing glueless connection to pipelined SSRAMs. The ZBT SRAM protocol is used allowing glueless connection to pipelined ZBT SRAMS.
1 Parity Selection
The RAM_EVEN_PAR bit selects even or odd parity for the RAM I/F as follows: RAM_EVEN_PAR 0 1 Function Odd parity is generated and checked. Even parity is generated and checked.
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11
INTERRUPTS The interrupt logic has several layers and can be sourced from any of eight blocks. The eight blocks are the UTOPIA block, the two RAM interface blocks, the four or one A1SP blocks and the Line Interface block. The top layer of the interrupt logic, the Master Interrupt Register (0x80000), indicates from which block the interrupt came from. Once the block is determined the processor can access the appropriate block to determine the interrupt cause. Figure 21 shows the registers in the interrupt tree. The microprocessor traverses the tree based on the value of individuals bits within each register. Figure 21 - Interrupt Hierarchy
MSTR_INTR_REG
Top Level
A1SPn_INTR_REG
SBIA_UR_REGn SBIA_OR_REGn
SBID_UR_REGn SBID_OR_REGn
2nd Level Utopia INTR RAM INTR
Line Interface Interrupt
A1SPn_TIDLE_FIFO
RCVn_STAT_FIFO
3rd Level
R_ERROR_STKY A1SPn Interrupts A1SPn Interrupts 4th Level
Interrupt and Status Registers Memory Map These registers indicate the current status of the device and any conditions that might require processor attention: Address 0x81000 Register Description Master Interrupt Register Register Mnemonic MSTR_INTR_REG
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Address
Register Description
Register Mnemonic A1SPn_INTR_REG A1SPn_STAT_REG A1SPn_TIDLE_FIFO A1SPn_RSTAT_FIFO MSTR_INTR_EN_REG A1SPn_INTR_EN A1SPn_RSTAT_EN
0x81010,...,13 A1SPn Interrupt Register 0x81020,...,23 A1SPn Status Register 0x81030,...,33 A1SPn Transmit Idle State FIFO 0x81040,...,43 A1SPn Receive Status FIFO 0x81100 0x81110,...,13 0x81140,...,43 0x81150,...,53 Master Interrupt Enable Register A1SPn Interrupt Enable Register A1SPn Receive Status FIFO Enable Register
A1SPn Receive Queue Error Enable A1SPn_RCV_Q_ERR_ EN
Note: In the AAL1gator-8 and AAL1gator-4, only the A1SP0 registers are used. 11.1 Master Interrupts The Master Interrupt Register (0x81000) is at the top of the Interrupt Tree. It indicates which lower level interrupt registers have interrupts pending. The UTOPIA Interface error bits and RAM parity error bits are cleared on read, the other bits are current status and will remain set as long as the underlying condition remains active. For bits which are cleared on read, a logic `0' indicates that no further interrupts of this type has been encountered while a logic `1' indicates that another such interrupt has been encountered. For bits which indicate current status, a logic `0' indicates that no interrupt is pending while a logic `1' indicates that the interrupt is still pending. The enable bits in the Master Interrupt Enable Register (0x81100) control the corresponding interrupt bits in the Master Interrupt Register (0x81000). When an enable bit in the Master Interrupt Enable Register (0x81100) is set to a logic `1', the corresponding error event from the Master Interrupt Register (0x81000) will cause the active low interrupt signal to the microprocessor, INTB, to go active. The following interrupts are at the top of the interrupt tree and have status and enable bits in the Master Interrupt Register (0x81000) and Master Interrupt Enable Register (0x81100) respectively. A bit type of RO specifies an interrupt bit that indicates current status while a bit type of R2C specifies an interrupt bit that is cleared on read. The interrupt description column describes the condition when the interrupt bit is a logic `1'.
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Bit (Position) A1SP0_INTR(0) A1SP1_INTR(1) A1SP2_INTR(2) A1SP3_INTR(3) RAM1_PAR_ERR(4) RAM2_PAR_ERR(5) UTOP_PAR_ERR(6) T_UTOP_FULL(7) T_UTOP_XFR_ERR(8)
Type RO RO RO RO R2C R2C R2C R2C R2C
Interrupt Description when Bit = `1' Interrupt pending from A1SP0. Read A1SP0_INTR_REG to determine cause. Interrupt pending from A1SP1. Read A1SP0_INTR_REG to determine cause. Interrupt pending from A1SP2. Read A1SP0_INTR_REG to determine cause. Interrupt pending from A1SP3. Read A1SP0_INTR_REG to determine cause. Parity encountered in RAM1 interface. Parity encountered in RAM2 interface. Parity encountered in UTOPIA interface. Transmit UTOPIA FIFO is full. If it is still full after a read, the bit will set again. The Transmit UTOPIA Interface was requested to send a cell when it did not have one available. UTOPIA loopback FIFO is full. If it is still full after a read, the bit will set again. A runt cell (less than 53 bytes) was received. An interrupt is pending related to the SBI Add Bus, also known as the Insert SBI bus. Read the Insert Master Interrupt Status Register (INS_MSTR_INT) to find the cause of the interrupt. An interrupt is pending related to the SBIDrop Bus, also known as the Extract SBI bus. Read the Extract Master Interrupt Status Register (EXT_MSTR_INT) to find the cause of the interrupt. An SBI Alarm is pending in either the SBI_ALARM_REGH or SBI_ALARM_REGL registers.
UTOP_LFIFO_FULL(9) R_UTOP_RUNT_CL(10) SBI_ADD_INTR(11)
R2C R2C RO
SBI_DROP_INTR(12)
RO
SBI_ALARM(13)
RO
Notes:
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*
The A1SP1_INTR, A1SP2_INTR , A1SP3_INTR , RAM2_PAR_ERR, SBI_ADD_INTR, SBI_DROP_INTR, and SBI_ALARM interrupts are not used in the AAL1gator-8 and AAL1gator-4. The RAM2_PAR_ERR is not used if the 2nd RAM interface is not needed for the AAL1gator-32.
*
11.2 UTOPIA Interrupts The UTOPIA block sources five interrupts directly to the Master Interrupt Register (0x81000). The five interrupts are Transmit UTOPIA FIFO full, Loopback FIFO full, UTOPIA parity error, runt cell error, and UTOPIA transfer error. The first interrupt indicates that the Transmit UTOPIA four cell FIFO has filled. The second interrupt indicates that the UTOPIA loopback FIFO has filled. The third interrupt indicates there was a parity error on the data received on the UTOPIA interface. The fourth interrupt indicates cell less than 53 bytes was detected. The fifth interrupt indicates the receive UTOPIA interface was requested to send a cell when it did not have one available. 11.3 RAM Interface Interrupts The two RAM interface blocks each source a parity error interrupt directly to the Master Interrupt Register. 11.4 Line Interface Interrupts The Line Interface sources three interrupts: SBI_DROP_INTR and SBI_ADD_INTR and SBI_ALARM_INTR. The SBI_DROP_INTR indicates there is an interrupt pending related to the SBI-Drop bus, also known as the Extract SBI bus. The Extract Master Interrupt Status Register needs to be read to determine the cause of the interrupt. The SBI_ADD_INTR indicates there is an interrupt pending related to the SBI-Add bus, also known as the Insert SBI bus. The Insert Master Interrupt Status Register needs to be read to determine the cause of the interrupt. The SBI_ALARM_INTR indicates that an alarm was detected on a link from the SBI. SBI_ALARM_REGH and SBI_ALARM_REGL registers will identify which link failed. Please see section 8 for the description of SBI alarm and interrupt registers. 11.5 A1SP Interrupts The A1SP blocks each source an interrupt to the Master Interrupt Register (0x81000). Within each A1SP block, the A1SPn interrupt register indicates the source of the interrupt within the A1SP block. Since many indications provided by the A1SP interrupt structure are per channel or per queue, there are 2 FIFOs
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provided for per channel indications. There are six possible sources of an interrupt for the A1SP_INTR_REG: A1SPn Receive Status FIFO not empty, A1SPn Transmit Idle State FIFO not empty, A1SPn Receive Status FIFO overflow, Transmit Idle State FIFO overflow, OAM interrupt, and Frame Advance FIFO overflow. The OAM interrupt indicates that the Receive OAM Queue is not empty. In other words, this interrupt can be thought of as an active low Receive OAM Queue Empty signal. The A1SPn Receive Status FIFO overflow, A1SP Transmit Idle State FIFO overflow, and Frame Advance FIFO overflow interrupts simply indicate that the FIFOs have overflowed. The A1SPn Receive Status FIFO not empty interrupt indicates the A1SPn Receive Status FIFO is not empty and the A1SPn Transmit Idle State FIFO not empty interrupts do the same. The next two sections discuss how these FIFOs operate. Since some of the conditions are transitory, the A1SPn_INTR_REG (0x81010, ...,13) captures whether the condition has occurred since the last time the register was read. The bits in this register are set upon entry into the indicated condition and are cleared when this register is read. If any of these conditions still exist the corresponding bit will not be set again until the condition ends and then occurs. The interrupt description column describes the condition when the bit in A1SPn_INTR_REG is a logic `1'. The condition does not exist if the bit is a logic `0'. Bit (Position) FR_ADV_FIFO_FULL(0) OAM_INTR(1) TIDLE_FIFO_EMPB(2) TIDLE_FIFO_FULL(3) RSTAT_FIFO_EMPB(4) RSTAT_FIFO_FULL(5) TALP_FIFO_FULL(6) Interrupt Description when Bit = `1' The Frame Advance FIFO has entered the full state since the last time the register was read. A1SPn has received a new OAM cell. The Transmit Idle State FIFO has entered the not empty state. The Transmit Idle State FIFO has entered the full state. The Receive Status FIFO has entered the not empty state. The Receive Status FIFO has entered the full state. The TALP FIFO has entered the full state.
Read the A1SPn_STAT_REG (0x81020, ..., 23) for current status. If any bit is set in this register and the corresponding enable bit is set in A1SPn_INTR_EN_REG (0x81110, ..., 13), the A1SPn_INTR bit will be set in MSTR_INTR_REG (0x81000). The interrupt description column in the table below describes the condition when the bit in A1SPn_STAT_REG is a logic `1'. The condition does not exist if the bit is a logic `0'.
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Bit (Position) FR_ADV_FIFO_FULL(0) OAM_INTR(1) TIDLE_FIFO_EMPB(2) TIDLE_FIFO_FULL(3) RSTAT_FIFO_EMPB(4) RSTAT_FIFO_FULL(5) TALP_FIFO_FULL(6)
Interrupt Description when Bit = `1' The Frame Advance FIFO is full. A1SPn has received a new OAM cell. The Transmit Idle State FIFO is not empty. The Transmit Idle State FIFO is full. The Receive Status FIFO is not empty. The Receive Status FIFO is full. The TALP FIFO is full.
11.5.1 A1SPn Receive Status FIFO The Receive Status FIFO (RCV_STAT_FIFO) consists of 64 entries and is contained internal to the chip. The FIFO is accessed using a single address. When the FIFO transitions from empty to not empty, the RSTAT_FIFO_EMPB bit in both the A1SPn_INTR_REG and the A1SPn_STAT_REG will go active. When there are no longer any entries in the FIFO, the STAT_FIFO_EMPB bit in the A1SPn_STAT_REG will go inactive. Each entry within the Interrupt FIFO indicates the queue responsible for the interrupt and one of four possible causes: DBCES bitmask change, exiting underrun, entering underrun, and receive queue error. The first cause reports a change in the bit mask for DBCES. The second two causes simply report a change in the underrun status, while the third cause indicates an error has occurred on the receive side. To find out the specific cause of the error, the processor should access the R_ERROR_STKY register for the queue responsible for the interrupt. The A1SPn Receive Status FIFO register (0x81040, ..., 43) is the read port of a 64 word FIFO that is used to capture receive status events on a first come first serve basis. If the FIFO overflows the RSTAT_FIFO_FULL bit will be set in the A1SPn_INTR_REG. The presence of data in this FIFO will set the RSTAT_FIFO_EMPB bit in the A1SPn_INTR_REG. The RSTAT_EN_REG (0x81140, ..., 43) controls whether the corresponding errors or status conditions cause an entry to be written into the RSTAT_FIFO. There is a separate RSTAT_FIFO for each A1SP block. The following bits are used to report error or status conditions:
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RSTAT_FIFO_REG Bit RECEIVE_QUEUE_ERR
Function An error or status condition occurred on the receive queue identified in QUEUE_NUMBER. Read sticky bit register for this queue to determine actual event. The queue identified by QUEUE_NUMBER just entered the underrun state. If the queue is in DBCES mode, this may also indicate that all channels have gone idle. The queue identified by QUEUE_NUMBER just exited the underrun state. This condition is only valid if DBCES mode has been enabled for this queue. If the bit is set it indicates that the bitmask for active channels has changed. Read R_CHAN_ACT in the R_QUEUE_TBL to determine current bit mask. The transmit line identified by QUEUE_NUMBER(7:5) entered a resync state. The receive line identified by QUEUE_NUMBER(7:5) entered a resync state. Identifies the queue on which the reported event occurred. Note that the queue number is modulus 256. The top two bits of the queue number will be the number of the A1SP block that is being read.
ENTER_UNDERRUN
EXIT_UNDERRUN BITMASK_CHANGE
T_LINE_RESYNC R_LINE_RESYNC QUEUE_NUMBER [7:0]
11.5.2 A1SPn Transmit Idle State FIFO The Transmit Idle State FIFO consists of 64 entries and is contained internal to the chip. The FIFO is accessed using a single address port. When the FIFO transitions from empty to not empty, the TX_IDLE_FIFO_EMPB bit in both the A1SPn_INTR_REG and the A1SPn_STAT_REG will go active. When there are no longer any entries in the FIFO, the Transmit Idle State FIFO not empty interrupt bit in the A1SPn_STAT_REG will go inactive. Each entry within the Transmit Idle State FIFO indicates the channel responsible for the interrupt and certain status information depending on the selected DBCES mode. The A1SPn_TIDLE_FIFO (0x81030, ..., 33) register is the read port of a 64 word FIFO that is used to indicate changes in the activity status (active or idle) on a given channel on a first come first serve basis. If the FIFO overflows the
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TX_IDLE_FIFO_FULL bit will be set in the A1SPn_INTR_REG. When this FIFO goes from an empty to a non-empty condition the TX_IDLE_FIFO_EMPB bit in the A1SPn_INTR_REG will be set. The presence of data in this FIFO will set the TX_IDLE_FIFO_EMPB bit in the A1SPn_STAT_REG. Read A1SPn_STAT_REG to determine when FIFO goes empty again. If idle detection is not enabled on a given channel then the channel will not write to this FIFO. The function of the CHAN_STATUS[15:0] bits is dependent on which of the two idle detection modes is used: automatic or processor. The idle detection mode is controlled by the value of IDLE_CFG_Ln_Cx for the respective line and channel number in the Idle Configuration Detection Table (see section 7). 11.5.2.1 Automatic Idle Detection with either CAS or Pattern Matching
In this mode when either CAS or Pattern Matching indicates a change in the active status of a channel, an entry will be written into the FIFO depending on the state of IDLE_CFG_Ln_Cx for that channel. Bits CHAN_STATUS[0] Function STATUS: When clear, indicates that the channel contained in the CHAN_NUM field is in the idle state. When set, indicates that the channel contained in the CHAN_NUM field is in the active state. CHAN_NUM [7:0]: This field indicates the channel that encountered a change in activity status.
CHAN_STATUS[15:8 ] 11.5.2.2
Processor Idle Detection
In this mode, any changes in the CAS value in either direction will cause an entry to be written to the FIFO if Processor Idle detection is enabled for this line. Note that filtering of CAS changes is only done once by the AAL1gator. If any additional filtering is required, this must be done in the external framers: Bits CHAN_STATUS[3:0] CHAN_STATUS[7:4] CHAN_STATUS[15:8 ] Function TX_CAS: This field indicates the current value of the transmit CAS ABCD bits. RX_CAS: This field indicates the current value of the receive CAS ABCD bits. CHAN_NUM [7:0]: This field indicates the channel that encountered a change in activity status.
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11.5.3 Receive Queue Error Enables The enable bits in the RCV_Q_ERR_EN (0x81150, ..., 53) register control what is done when R_ERROR_STKY bits are set in the R_QUEUE_TBL. It controls which types of error/status conditions cause the RECEIVE_QUEUE_ERR indication in the RCVn_STAT_FIFO to be set. All queues are configured the same way. Only the first enabled condition which occurs for a given queue will cause an entry to be made in the RCVn_STAT_FIFO until the sticky bit register is cleared. So usually you should only enable bits that will not occur normally. The default configuration is as follows: Bit UNDERRUN OVERRUN PTR_MISMATCH RESUME SRTS_UNDERRUN SRTS_RESUME PTR_PARITY_ERR SN_CELL_DROP POINTER_SEARCH ALLOC_TBL_BLANK PTR_RULE_ERROR DBCES_BM_ERR CELL_RECEIVED Reserved Register RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) RCV_Q_ERR_EN (0x81150, ..., 53) Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
POINTER_RECEIVED RCV_Q_ERR_EN (0x81150, ..., 53) FORCED_UNDERRUN RCV_Q_ERR_EN (0x81150, ..., 53)
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PROGRAMMER'S GUIDE
12
IDLE CHANNEL DETECTION CONFIGURATION AND STATUS The following registers control how idle channel detection is configured for the AAL1gator and indicate active/idle channel status for all channels on the chip. Offset 0x000 - 0x00F 0x010 - 0x01F 0x100 0x1FF 0x200 0x20F 0x210 - 0x217 0x220 0x300 - 0x3FF Register Description A1SP n Receive Channel Active Table A1SP n Receive Pending Channel Table A1SP n Change Pointer Table A1SP n Transmit Channel Active Table A1SP n Pattern Matching Line Configuration A1SP n Idle Detection Configuration Table A1SP n CAS/Pattern Matching Configuration Table Register Mnemonic RX_ACTIVE_TBLn RX_PENDING_TBLn RX_CHANGE_PTRn TX_ACTIVE_TBLn PAT_MTCH _CFGn IDLE_CFG_TBLn CAS_P_CFG_TBLn
The base addresses for Idle Channel registers for the four A1SPs are as follows: A1SP 0 1 2 3 Base Address 0x82000 0x82400 0x82800 0x82C00
Note: In the AAL1gator-8 and AAL1gator-4, only the A1SP 0 registers are used. 12.1 Receive Channel Active Table The Receive Channel Active Table contains the receive active channel status for A1SP n block which contains m lines of 32 channels (m x 32 channels total)
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PROGRAMMER'S GUIDE
where m = 8 for the AAL1gator-32 and AAL1gator-8 and m = 4 for the AAL1gator-4. Therefore, lines 4 to 7 are not used in the AAL1gator-4. The status for each channel is composed of a 1 bit field (RX_CHAN_ACTIVE) and therefore each word contains the status for 16 channels. The structure of the table is shown below. LINE = OFFSET (MOD 32) / 2 CHANNEL (ADDRESS) = OFFSET (MOD 2) CHANNEL (BIT LOCATION) = CHANNEL (MOD 16)
Addr. Offset 0x000 0x001 ... ... 0x00E 0x00F
Line 0 0 ... ... 7 7
Channel RX_CHAN_ACTIVE[15:0] RX_CHAN_ACTIVE[31:16] RX_CHAN_ACTIVE[15:0] RX_CHAN_ACTIVE[31:16] RX_CHAN_ACTIVE[15:0] RX_CHAN_ACTIVE[31:16]
The one bit RX_CHAN_ACTIVE[n] field indicates the active status of the receive channel based on DBCES bit mask. This field is only valid if DBCES is enabled for the queue which is associated with this channel. On read: RX_CHAN_ACTIVE[n] 0 1 12.2 Receive Pending Table The A1SP n RX Pending Table contains the receive pending channel status for A1SP n block which contains m lines of 32 channels (m x 32 channels total) where m = 8 for the AAL1gator-32 and AAL1gator-8 and m = 4 for the AAL1gator-4. Therefore, lines 4 to 7 are not used in the AAL1gator-4. The status for each channel is composed of a 1 bit field (RX_PENDING) and Function Receive Channel n on the particular A1SP and line is inactive. Receive Channel n on the particular A1SP and line is active.
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PROGRAMMER'S GUIDE
therefore each word contains the status for 16 channels. The structure of the table is shown below. LINE = OFFSET (MOD 32) / 2 CHANNEL (ADDRESS) = OFFSET (MOD 2) CHANNEL (BIT LOCATION) = CHANNEL (MOD 16)
Addr. Offset 0x000 0x001 .. .. 0x00E 0x00F
Line 0 0 .... .... 7 7
Channel RX_PENDING [15:0] RX_PENDING [31:16] RX_PENDING [15:0] RX_PENDING [31:16] RX_PENDING [15:0] RX_PENDING [31:16]
The one bit RX_PENDING[n] field indicates the change pending status of the receive channel based on DBCES bit mask. This field is only valid if DBCES is enabled for the queue which is associated with this channel. This bit is set when the RALP detects a change in the bit mask, and is reset when the RFTC updates the active table with the pending change. On read: RX_PENDING[n] 0 1 Function No change in state is pending for this channel. A state change is pending for this channel.
12.3 Receive Change Pointer Table The RX Change Pointer Table contains the frame pointers, indicating in what frame a channel should change its active state. The new active state is stored along with the frame pointer. This table is generated by the RALP when it gets the bit mask updates in DBCES mode and consumed by the RTFC. When the RFTC gets to the frame specified in the pointer, if the pending bit is set in the pending table, the RFTC updates the active table and plays out the appropriate data depending upon the state of the channel. The structure of the table is shown below. Note that lines 4-7 are not used in the AAL1gator-4.
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PROGRAMMER'S GUIDE
This table is for chip use only and should not be modified after initialization. Initialize to all "0"s. LINE = OFFSET (MOD 256) / 32 CHANNEL (ADDRESS) = OFFSET (MOD 32)
Addr. Offset 0x100 0x101 .. .. 0x1FE 0x1FF Bits
Line 0 0 ... ... 7 7
Channel CHANGE_PTR_0 CHANGE_PTR_1 ... ... CHANGE_PTR _30 CHANGE_PTR _31 Function FRAME_PTR: Indicates the value of frame pointer in which the active status of the channel should change to the value indicated in ACTIVE. ACTIVE: Indicates the state which should become current at the frame indicated by FRAME_PTR. When set, the channel should change to an inactive state. When low, the channel should change to an active state.
CHANGE_PTR[8:0]
CHANGE_PTR [9]
12.4 Transmit Channel Active Table The A1SP n TX Channel Active Table contains the transmit active channel status for each A1SP block which each contain m lines of 32 channels (4 x m x 32 channels total) where m = 8 for the AAL1gator-32 and AAL1gator-8 and m = 4 for the AAL1gator-4. Therefore, lines 4 to 7 are not used in the AAL1gator-4. The status for each channel is composed of a 1 bit field (TX_CHAN_ACTIVE) and therefore each word contains the status for 16 channels. The structure of the table is shown below. This table should be initialized to all `0's. A1SP = OFFSET / 16 LINE = OFFSET (MOD 32) / 2
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PROGRAMMER'S GUIDE
CHANNEL (ADDRESS) = OFFSET (MOD 2) CHANNEL (BIT LOCATION) = CHANNEL (MOD 16)
Addr. Offset 0x200 0x201 ... ... 0x20E 0x20F
Line 0 0 ... ... 7 7
Channel TX_CHAN_ACTIVE[15:0] TX_CHAN_ACTIVE[31:16] TX_CHAN_ACTIVE[15:0] TX_CHAN_ACTIVE[31:16] TX_CHAN_ACTIVE[15:0] TX_CHAN_ACTIVE[31:16]
The one bit TX_CHAN_ACTIVE[n] field indicates the active status of the channel. This field is only valid if IDLE_CFG for the associated channel is not equal to "00" (disabled). If IDLE_CFG is equal to "10" (Automatic, CAS) or "11" (Automatic, Pattern) then this field is read only and is updated by the AAL1gator. If IDLE_CFG equals "01" (processor) then the processor activates and deactivates channels by writing this bit. On read/write: TX_CHAN_ACTIVE[n] 0 1 Channel is inactive. Channel is active. Function
Note: Channels within a 16-bit word should not mix automatic detection with processor IDLE_CFG modes because there can be contention in updating these fields. 12.5 Pattern Matching Line Configuration The A1SP n Pattern Matching Line Configuration table contains the configuration for each line that is running in pattern matching idle detection mode. When the received pattern matches the programmed pattern within the bounds set within this table; the channel is considered to be idle. Please note that lines 4 to 7 are not used in the AAL1gator-4. A1SP = OFFSET / 8 LINE = OFFSET
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PROGRAMMER'S GUIDE
Addr. Offset 0x210 0x210 ... ... 0x217 0x217
Line 0 0 .... .... 7 7
Bit 15:8 7:0
Channel Reserved INTVL_LEN .... ....
15:8 7:0
Reserved INTVL_LEN
The INTVL_LEN[7:0] field defines the interval length in increments of 12 ms (T1) or 16 ms (E1). The interval length is calculated by taking the number from this field, adding 1, and multiplying the result by 12/16 ms ((INTVL_LEN + 1) * 12/16 ms). 12.6 Idle Detection Configuration Table The A1SP n Idle Detection Configuration Table contains the idle detection configuration for the A1SP n block which contains m lines where m = 8 for the AAL1gator-32 and AAL1gator-8 and m = 4 for the AAL1gator-4. Therefore, IDLE_CFG_4 through IDLE_CFG_7 are not used in the AAL1gator-4. The configuration for each line is composed of a 2 bit field (IDLE_CFG) and therefore the register contains the configuration for up to 8 lines. The structure of the table is shown below. Addr. Offset 0x220 Line Configuration IDLE_CFG_m
The two-bit IDLE_CFG_m field defines the idle detection mode. Selection of the four possible modes is shown below: IDLE_CFG_m 00 01 10 11 Idle Detection Mode Idle Detection Disabled. Processor controlled activation/deactivation of channels. Automatic activation/deactivation of channels using CAS matching. Automatic activation/deactivation of channels using pattern matching.
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12.7 CAS/Pattern Matching Configuration The A1SP n CAS/Pattern Matching Configuration Table contains the configuration fields for automatic idle channel detection or processor idle detection depending on the value of IDLE_CFG. The A1SP block contains m lines of 32 channels (m x 32 channels total per A1SP) where m = 8 for the AAL1gator-32 and AAL1gator-8 and m = 4 for the AAL1gator-4. Therefore, lines 4 to 7 are not used in the AAL1gator-4. The function of these fields changes depending on whether IDLE_CFG indicates CAS mode, Pattern Matching, or Processor Idle Detection mode for the associated channel. The configuration field for each channel is composed of a 16 bit field (AUTO_CONFIG/PROC_CONFIG) and therefore each word contains the status for 1 channel. The structure of the table is shown below. LINE = OFFSET (MOD 256) / 32 CHANNEL (ADDRESS) = OFFSET (MOD 32)
Addr. Offset 0x300 0x301 ... ... 0x3FE 0x3FF
Line 0 0 ... ... 7 7
Channel AUTO_CONFIG_0/PROC_CONFIG_0 AUTO_CONFIG_1/PROC_CONFIG_1 ... ... AUTO_CONFIG_30/PROC_CONFIG_30 AUTO_CONFIG_31/PROC_CONFIG_31
AUTO_CONFIG_n has two different formats. If IDLE_CFG = "10" (CAS mode) it has one format. If IDLE_CFG = "11" it has a different format. If IDLE_CFG = "00" AUTO_CONFIG is reserved and should not be written. If IDLE_CFG = "01" the field uses the PROC_CONFIG_n format which is different than the AUTO_CONFIG_n format. 12.7.1 CAS Matching Format The CAS matching format is used when IDLE_CFG_m = "10" and is described in the following table:
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PROGRAMMER'S GUIDE
Bit 15:12
Function RX_MASK
Description These bits are used as a mask on the RX_CAS field. When a bit is set in these mask fields the bit will not be factored into the pattern matching function and therefore will be considered a "don't care" bit. These bits are used as a mask on the TX_CAS field. When a bit is set in these mask fields the bit will not be factored into the pattern matching function and therefore will be considered a "don't care" bit. Indicates the value of CAS that when received from the ATM network indicates an idle condition. This value will be masked by RX_MASK. Indicates the value of CAS that when received on the line indicates an idle condition. This value will be masked by TX_MASK.
11:8
TX_MASK
7:4
RX_CAS
3:0
TX_CAS
12.7.2 Pattern Matching Format The Pattern Matching Format is used when IDLE_CFG_m = "11" and is described in the following table: Bit 15:8 Function PAT_MASK Description When a bit is set in this mask field the bit will not be factored into the pattern matching function and therefore will be considered a "don't care" bit. When this programmed pattern matches the received byte for the associated channel, the channel is considered to be idle. The conditions which qualify a match are controlled by the PAT_MTCH_CFG register.
7:0
IDLE_PATTER N
12.7.3 Processor Idle Detection Format The Processor Idle Detection Format is used when IDLE_CFG_m = "01" and is described in the following table:
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PROGRAMMER'S GUIDE
Bit 15:12
Function RX_MASK
Description These bits are used as a mask on the RX_CAS field. Only changes in unmasked CAS bits will cause an interrupt to the processor. These bits are used as a mask on the TX_CAS field. Only changes in unmasked CAS bits will cause an interrupt to the processor. Reserved for internal use. Initialize to `0'.
11:8
TX_MASK
7:0
Reserved
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-199-1820 (P2) Issue date: April 2001
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